Analog Devices ADSP-TS201S specifications Timing Specifications, General AC Timing

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ADSP-TS201S

TIMING SPECIFICATIONS

With the exception of DMAR3–0, IRQ3–0, TMR0E, and FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSP- TS201S processor has few calculated (formula-based) values. For information on ac timing, see General AC Timing. For information on link port transfer timing, see Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing on Page 30.

General AC Timing

Timing is measured on signals when they cross the 1.25 V level as described in Figure 15 on Page 29. All delays (in nanosec- onds) are measured between the point that the first signal reaches 1.25 V and the point that the second signal reaches 1.25 V.

Table 21. AC Asynchronous Signal Specifications

The general ac timing data appears in Table 22 and Table 29. All ac specifications are measured with the load specified in Figure 36 on Page 38, and with the output drive strength set to strength 4. In order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to Figure 37 on Page 38 through Figure 44 on Page 39 (Rise and Fall Time vs. Load Capacitance) and Figure 45 on Page 39 (Out- put Valid vs. Load Capacitance and Drive Strength).

The ac asynchronous timing data for the IRQ3–0, DMAR3–0, FLAG3–0, and TMR0E pins appears in Table 21.

 

Name

Description

Pulse Width Low (Min)

Pulse Width High (Min)

 

 

1

 

Interrupt Request

2 × tSCLK ns

2 × tSCLK ns

 

IRQ3–0

 

 

1

DMA Request

2 × tSCLK ns

2 × tSCLK ns

 

DMAR3–0

 

FLAG3–02

FLAG3–0 Input

2×tSCLK ns

2×tSCLK ns

 

TMR0E3

Timer 0 Expired

4×tSCLK ns

—

1These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.

2 For output specifications on FLAG3–0 pins, see Table 29.

3 This pin is a strap option. During reset, an internal resistor pulls the pin low.

Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time

 

 

Grade = 060 (600 MHz)

Grade = 050 (500 MHz)

 

Parameter

Description

Min

Max

Min

Max

Unit

1

Core Clock Cycle Time

1.67

12.5

2.0

12.5

ns

tCCLK

1CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (tSCLK) divided by the system clock ratio (SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 46.

tCCLK

CCLK

Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time

Rev. C Page 24 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 nsDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceDMA Controller Host InterfaceMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports LvdsPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Evaluation KIT Additional InformationPin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationPin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC MakesPin Definitions-External Port Sdram Controller LdqmHdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionPin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionPin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Operating Conditions SclkvrefElectrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand InformationTiming Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxDS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsSdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3NDS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNSurface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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