Analog Devices ADSP-TS201S Impedance Control Selection, Drive Strength/Output Impedance Selection

Page 19

ADSP-TS201S

Table 13. Impedance Control Selection

CONTROLIMP1-0

Driver Mode

00

(recommended)

Normal

01

 

Reserved

10

(default)

A/D Mode

11

 

Reserved

Table 14. Drive Strength/Output Impedance Selection

DS2–0

Drive

Output

Pins

Strength1

Impedance 2

000

Strength 0 (11.1%)

26 Ω

001

Strength 1 (23.8%)

32 Ω

010

Strength 2 (36.5%)

40 Ω

011

Strength 3 (49.2%)

50 Ω

100

Strength 4 (61.9%)

62 Ω

101 (default)

Strength 5 (74.6%)

70 Ω

110

Strength 6 (87.3%)

96 Ω

111

Strength 7 (100%)

120 Ω

1CONTROLIMP1 = 0, A/D mode disabled.

2 CONTROLIMP1 = 1, A/D mode enabled.

Table 15. Pin Definitions—Power, Ground, and Reference

Signal

Type

Term

 

Description

VDD

P

na

 

VDD pins for internal logic.

VDD_A

P

na

 

VDD pins for analog circuits. Pay critical attention to bypassing this supply.

VDD_IO

P

na

 

VDD pins for I/O buffers.

VDD_DRAM

P

na

 

VDD pins for internal DRAM.

VREF

I

na

 

Reference voltage defines the trip point for all input buffers, except SCLK,

 

 

RST_IN,

 

 

 

 

POR_IN,

 

IRQ3–0,

FLAG3–0,

DMAR3–0,

ID2–0, CONTROLIMP1–0, LxDATO3–0P/N,

 

 

 

 

LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and

TRST.

VREF can be

 

 

 

 

connected to a power supply or set by a voltage divider circuit as shown in Figure 6.

 

 

 

 

For more information, see Filtering Reference Voltage and Clocks on Page 10.

SCLK_VREF

I

na

System Clock Reference. Connect this pin to a reference voltage as shown in Figure 7.

 

 

 

 

For more information, see Filtering Reference Voltage and Clocks on Page 10.

VSS

G

na

 

Ground pins.

NC

—

nc

 

No Connect. Do not connect these pins to anything (not to any supply, signal, or each

 

 

 

 

other). These pins are reserved and must be left unconnected.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Rev. C Page 19 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S FIR filter per real tap 83 ns General-Purpose Algorithm Benchmarks at 600 MHzClock Benchmark Speed CyclesData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Flexible Instruction Set Program SequencerDSP Memory Interrupt ControllerInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceSdram Controller DMA ControllerHost Interface Multiprocessor InterfaceDMA controller provides these additional features Link Ports Lvds Timer and GENERAL-PURPOSE I/OReset and Booting No Boot, Run from Memory AddressesFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITRatio Pin Definitions-Clocks and ResetSignal Type Term Description Sclk RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeMakes Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Sample the data instead of the TigerSHARCSDA10 Pin Definitions-External Port Sdram ControllerLdqm HdqmPin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerDS1 Pin Definitions-Link PortsCONTROLIMP0 CONTROLIMP1Impedance Control Selection Pin Definitions-Power, Ground, and ReferenceDriver Mode DS2-0 Drive Output Pins Strength ImpedanceType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsVIN Max VIN Min Cycle2 Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage Maximum DutyPackage Brand Information Package InformationESD Sensitivity Absolute Maximum RatingsReference Clocks-Core Clock Cclk Cycle Time Timing SpecificationsAC Asynchronous Signal Specifications General AC TimingParameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap SYS 9 DS2-0 Static Pins-Must Be ConstantStrap Pins Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0VOD Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Parameter Condition Typical Unit Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Environmental ConditionsBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0DATI3N Sdcke SCLKRAT1L0ACKO L0DATI1NL1CLKINN DS2 Enedreg TCKID2 TDI TMR0E DS1 CONTROLIMP1 TDO FLAG3Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Surface Mount DesignBGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad SizeOrdering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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