Analog Devices ADSP-TS201S specifications Power-Up Timing1, Power-Up Reset Timing

Page 26

ADSP-TS201S

Table 25. Power-Up Timing1

Parameter

 

Min

Max

Unit

Timing Requirement

 

 

 

tVDD_DRAM

VDD_DRAM Stable After VDD, VDD_A, VDD_IO Stable

>0

 

ms

1For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing.

VDD

VDD_A

VDD_IO

tVDD_DRAM

VDD_DRAM

Figure 12. Power-Up Timing

Table 26. Power-Up Reset Timing

Parameter

 

 

 

 

 

 

Min

Max

Unit

Timing Requirements

 

 

 

tRST_IN_PWR

 

 

Deasserted After VDD, VDD_A, VDD_IO, VDD_DRAM, SCLK, and Static/

 

 

 

RST_IN

 

 

 

 

Strap Pins Stable

2

 

ms

1

 

 

 

 

 

 

 

 

 

TRST Asserted During Power-Up Reset

100 × tSCLK

 

ns

tTRST_IN_PWR

 

Switching Characteristic

 

 

 

tRST_OUT_PWR

 

Deasserted After

 

Deasserted

1.5

 

ms

RST_OUT

RST_IN

 

1Applies after VDD, VDD_A, VDD_IO, VDD_DRAM, and SCLK are stable and before RST_IN deasserted.

RST_IN

RST_OUT

TRST

SCLK, VDD, VDD_A, VDD_IO, VDD_DRAM

STATIC/STRAP PINS

tRST_IN_PWR

tTRST_IN_PWR

tRST_OUT_PWR

Figure 13. Power-Up Reset Timing

Rev. C Page 26 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsDual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsDevelopment Tools Power DomainsFiltering Reference Voltage and Clocks Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionPin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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