Analog Devices ADSP-TS201S specifications AC Signal Specifications, OutputDisable Max

Page 28

ADSP-TS201S

Table 29. AC Signal Specifications

(All values in this table are in nanoseconds.)

Name

Description

ADDR31–0

External Address Bus

DATA63–0

External Data Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Select HOST Line

MSH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Select SDRAM Lines

MSSD3–0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Select for Static Blocks

MS1–0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Read

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Low Word

WRL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write High Word

WRH

ACK

Acknowledge for Data High to Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Acknowledge for Data Low to High

SDCKE

SDRAM Clock Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row Address Select

RAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Address Select

CAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM Write Enable

SDWE

LDQM

Low Word SDRAM Data Mask

HDQM

High Word SDRAM Data Mask

SDA10

SDRAM ADDR10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Host Bus Request

HBR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Host Bus Grant

HBG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Back Off Request

BOFF

 

 

 

 

 

 

 

 

 

 

 

 

 

Bus Lock

BUSLOCK

 

 

 

 

 

 

 

 

 

 

 

 

Burst Pin

BRST

 

 

 

 

 

 

 

 

 

 

 

Multiprocessing Bus Request Pins

BR7–0

 

 

 

 

 

 

 

 

 

 

Bus Master Debug Aid Only

BM

 

 

 

 

 

 

 

 

 

I/O Read Pin

IORD

 

 

 

 

 

 

 

 

I/O Write Pin

IOWR

 

 

 

 

 

 

 

I/O Enable Pin

IOEN

 

 

 

 

 

 

Core Priority Access High to Low

CPA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core Priority Access Low to High

 

 

 

 

 

DMA Priority Access High to Low

DPA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA Priority Access Low to High

 

 

 

 

 

Boot Memory Select

BMS

FLAG3–02

FLAG Pins

 

 

 

3, 4

Global Reset Pin

RST_IN

TMS

Test Mode Select (JTAG)

TDI

Test Data Input (JTAG)

TDO

Test Data Output (JTAG)

 

 

3, 4

Test Reset (JTAG)

TRST

 

7

Emulation High to Low

EMU

ID2–08

Static Pins—Must Be Constant

CONTROLIMP1–08

Static Pins—Must Be Constant

SetupInput (Min)

HoldInput (Min)

OutputValid (Max)

OutputHold (Min)

OutputEnable (Min)

OutputDisable

(Max)

Reference Clock

 

 

 

 

1

1

 

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.0

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

3.6

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.2

0.9

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

—

—

—

—

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

—

—

—

—

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

—

—

 

SCLK

—

—

4.0

1.0

—

—

 

SCLK

—

—

4.0

1.0

1.0

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

1.5

0.5

4.0

1.0

0.75

2.0

 

SCLK

1.5

0.5

29.5

2.0

0.75

2.0

 

SCLK

1.5

0.5

4.0

1.0

0.75

2.0

 

SCLK

1.5

0.5

29.5

2.0

0.75

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

—

—

4.0

1.0

1.15

2.0

 

SCLK

1.5

2.5

—

—

—

—

 

SCLK5

1.5

0.5

—

—

—

—

 

TCK

1.5

0.5

—

—

—

—

 

TCK

—

—

4.0

1.0

0.75

2.0

 

TCK6

1.5

0.5

—

—

—

—

 

TCK

—

—

5.5

2.0

1.15

4.0

 

TCK or SCLK

—

—

—

—

—

—

 

—

—

—

—

—

—

—

 

—

 

 

 

 

 

 

 

 

Rev. C Page 28 of 48 December 2006

Page 27 Page 29
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Page 27 Page 29
Contents ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceDMA Controller Host InterfaceMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Evaluation KIT Additional InformationPin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationPin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC MakesPin Definitions-External Port Sdram Controller LdqmHdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionPin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Operating Conditions SclkvrefElectrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand InformationTiming Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxDS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsSdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3NDS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNSurface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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