Analog Devices ADSP-TS201S specifications Normal Reset Timing, On-Chip Dram Refresh1

Page 27

ADSP-TS201S

Table 27. Normal Reset Timing

Parameter

 

 

 

 

 

Min

Max

Unit

Timing Requirements

 

 

 

tRST_IN

 

Asserted

2

 

ms

RST_IN

 

tSTRAP

 

Deasserted After Strap Pins Stable

1.5

 

ms

RST_IN

 

Switching Characteristic

 

 

 

tRST_OUT

 

Deasserted After

 

Deasserted

1.5

 

ms

RST_OUT

RST_IN

 

RST_IN

RST_OUT

STRAP PINS

tRST_IN

tRST_OUT

tSTRAP

Figure 14. Normal Reset Timing

Table 28. On-Chip DRAM Refresh1

Parameter

 

Min

Max

Unit

Timing Requirement

 

 

 

tREF

On-chip DRAM Refresh Period

 

1.56

μs

1For more information on setting the refresh rate for the on-chip DRAM, refer to the ADSP-TS201 TigerSHARC Processor Programming Reference.

Rev. C Page 27 of 48 December 2006

Page 26 Page 28
Image 27
Page 26 Page 28
Contents ADSP-TS201S ADSP-TS201S FIR filter per real tap 83 ns General-Purpose Algorithm Benchmarks at 600 MHzClock Benchmark Speed CyclesDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Flexible Instruction Set Program SequencerDSP Memory Interrupt ControllerInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceSdram Controller DMA ControllerHost Interface Multiprocessor InterfaceDMA controller provides these additional features Link Ports Lvds Timer and GENERAL-PURPOSE I/OReset and Booting No Boot, Run from Memory AddressesPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Additional Information Evaluation KITRatio Pin Definitions-Clocks and ResetSignal Type Term Description Sclk RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeMakes Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Sample the data instead of the TigerSHARCSDA10 Pin Definitions-External Port Sdram ControllerLdqm HdqmPin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerDS1 Pin Definitions-Link PortsCONTROLIMP0 CONTROLIMP1Impedance Control Selection Pin Definitions-Power, Ground, and ReferenceDriver Mode DS2-0 Drive Output Pins Strength ImpedancePin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Sclkvref Operating ConditionsVIN Max VIN Min Cycle2 Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage Maximum DutyPackage Brand Information Package InformationESD Sensitivity Absolute Maximum RatingsReference Clocks-Core Clock Cclk Cycle Time Timing SpecificationsAC Asynchronous Signal Specifications General AC TimingParameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap SYS 9 DS2-0 Static Pins-Must Be ConstantStrap Pins Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0VOD Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Parameter Condition Typical Unit Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Environmental ConditionsBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0DATI3N Sdcke SCLKRAT1L0ACKO L0DATI1NL1CLKINN DS2 Enedreg TCKID2 TDI TMR0E DS1 CONTROLIMP1 TDO FLAG3Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Surface Mount DesignBGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad SizeTemperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
Top Page Image Contents