Analog Devices ADSP-TS201S specifications Output Enable Time, Capacitive Loading

Page 38

ADSP-TS201S

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. The time for the voltage on the bus to ramp by ΔV is dependent on the capacitive load, CL, and the drive current, ID. This ramp time can be approximated by the following equation:

tRAMP = (CLΔV) ⁄ ID

The output enable time tENA is the difference between

tMEASURED_ENA and tRAMP as shown in Figure 35. The time

tMEASURED_ENA is the interval from when the reference signal switches to when the output voltage ramps ΔV from the mea-

sured three-stated output level. tRAMP is calculated with test load CL, drive current ID, and with ΔV equal to 0.4 V.

Capacitive Loading

Output valid and hold are based on standard capacitive loads: 30 pF on all pins (see Figure 36). The delay and hold specifica- tions given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. Figure 37 through Figure 44 show how output rise time varies with capac- itance. Figure 45 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 37.) The graphs of Figure 37 through Figure 45 may not be linear outside the ranges shown.

TO

50Ω

OUTPUT

1.25V

PIN

30pF

 

Figure 36. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

 

 

 

 

 

STRENGTH 0

 

 

 

 

 

25

 

 

 

(VDD_IO = 2.5V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(ns)

20

 

 

 

 

 

 

 

 

 

 

TIMES

 

 

 

 

 

 

 

 

 

 

 

FALL TIME

 

 

 

 

 

 

 

FALL

15

 

 

 

 

 

 

 

Y = 0.251x + 4.2245

 

 

 

 

 

 

 

 

 

 

 

 

 

AND

10

 

 

 

 

 

 

 

 

 

 

RISE

 

 

 

RISE TIME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y = 0.259x + 3.0842

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

0

10

20

30

40

50

60

70

80

90

100

 

0

 

 

 

 

LOAD CAPACITANCE (pF)

 

 

 

Figure 37. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 0

 

 

 

 

 

 

STRENGTH 1

 

 

 

 

 

25

 

 

 

(VDD_IO = 2.5V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(ns)

 

 

 

 

 

 

 

 

 

 

 

FALLTIMES

20

 

 

 

 

 

 

 

 

 

 

15

 

 

FALL TIME

 

 

 

 

 

AND

 

 

 

 

 

 

 

 

 

 

 

Y = 0.1527x + 0.7485

 

 

 

 

RISE

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

RISE TIME

 

 

 

 

 

 

 

 

Y = 0.1501x + 0.05

 

 

 

 

 

 

 

 

 

 

 

 

0

10

20

30

40

50

60

70

80

90

100

 

0

 

 

 

 

LOAD CAPACITANCE (pF)

 

 

 

Figure 38. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 1

 

 

 

 

 

 

STRENGTH 2

 

 

 

 

 

25

 

 

 

 

(VDD_IO = 2.5V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(ns)

 

 

 

 

 

 

 

 

 

 

 

TIMES

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ANDFALL

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FALL TIME

 

 

 

 

RISE

10

 

 

 

 

 

 

 

 

 

 

Y = 0.0949x + 0.8112

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISE TIME

 

 

 

 

 

 

 

 

Y = 0.0861x + 0.4712

 

0

10

20

30

40

50

60

70

80

90

100

 

0

 

 

 

 

LOAD CAPACITANCE (pF)

 

 

 

Figure 39. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 2

STRENGTH 3

(VDD_IO = 2.5V)

 

25

 

 

 

 

 

 

 

 

 

 

(ns)

 

 

 

 

 

 

 

 

 

 

 

TIMES

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ANDFALL

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FALL TIME

 

 

 

 

RISE

10

 

 

 

 

 

 

 

 

 

 

Y = 0.0691x + 1.1158

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISE TIME

 

 

 

 

 

 

 

 

 

Y = 0.06x + 1.1362

 

 

0

10

20

30

40

50

60

70

80

90

100

 

0

 

 

 

 

LOAD CAPACITANCE (pF)

 

 

 

Figure 40. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 3

Rev. C Page 38 of 48 December 2006

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Page 37 Page 39
Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsDual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsDevelopment Tools Power DomainsFiltering Reference Voltage and Clocks Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionPin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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