Analog Devices ADSP-TS201S specifications Pin Definitions-External Port Bus Controls, Ack T/Od

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ADSP-TS201S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 5. Pin Definitions—External Port Bus Controls

 

 

 

 

 

 

 

 

 

 

Signal

Type

Term

 

Description

 

 

 

ADDR31–0

I/O/T

nc

Address Bus. The DSP issues addresses for accessing memory and peripherals on

 

 

 

 

 

 

 

 

 

 

(pu_ad)

 

these pins. In a multiprocessor system, the bus master drives addresses for accessing

 

 

 

 

 

 

 

 

 

 

 

 

internal memory or I/O processor registers of other ADSP-TS201S processors. The DSP

 

 

 

 

 

 

 

 

 

 

 

 

inputs addresses when a host or another DSP accesses its internal memory or I/O

 

 

 

 

 

 

 

 

 

 

 

 

processor registers.

 

DATA63–0

I/O/T

nc

External Data Bus. The DSP drives and receives data and instructions on these pins.

 

 

 

 

 

 

 

 

 

 

(pu_ad)

 

Pull-up or pull-down resistors on unused DATA pins are unnecessary.

 

 

 

 

 

 

 

 

 

 

I/O/T

epu1

 

Memory Read.

 

 

 

 

 

 

 

is asserted whenever the DSP reads from any slave in the system,

RD

RD

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

excluding SDRAM. When the DSP is a slave,

RD

 

is an input and indicates read trans-

 

 

 

 

 

 

 

 

 

 

 

 

 

actions that access its internal memory or universal registers. In a multiprocessor

 

 

 

 

 

 

 

 

 

 

 

 

 

system, the bus master drives

 

 

 

 

changes concurrently with ADDR pins.

 

 

 

 

 

 

 

 

 

 

 

 

RD.

RD

 

 

 

 

 

 

 

 

 

I/O/T

epu1

 

Write Low.

 

 

 

 

 

 

is asserted in two cases: when the ADSP-TS201S processor writes to

 

 

WRL

WRL

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

an even address word of external memory or to another external bus agent; and when

 

 

 

 

 

 

 

 

 

 

 

 

 

the ADSP-TS201S processor writes to a 32-bit zone (host, memory, or DSP

 

 

 

 

 

 

 

 

 

 

 

 

 

programmed to 32-bit bus). An external master (host or DSP) asserts

WRL

for writing

 

 

 

 

 

 

 

 

 

 

 

 

 

to a DSP’s low word of internal memory. In a multiprocessor system, the bus master

 

 

 

 

 

 

 

 

 

 

 

 

 

drives

 

 

 

 

 

 

 

 

 

 

 

changes concurrently with ADDR pins. When the DSP is a slave,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRL.

WRL

WRL

 

 

 

 

 

 

 

 

 

 

 

 

 

is an input and indicates write transactions that access its internal memory or

 

 

 

 

 

 

 

 

 

 

 

 

 

universal registers.

 

 

 

 

 

 

 

 

I/O/T

epu1

 

Write High.

 

 

 

 

 

is asserted when the ADSP-TS201S processor writes a long word

WRH

WRH

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

(64 bits) or writes to an odd address word of external memory or to another external

 

 

 

 

 

 

 

 

 

 

 

 

 

bus agent on a 64-bit data bus. An external master (host or another DSP) must assert

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system,

 

 

 

 

 

 

 

 

 

 

 

 

 

WRH

 

 

 

 

 

 

 

 

 

 

 

 

 

the bus master drives

WRH.

 

 

WRH

changes concurrently with ADDR pins. When the

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP is a slave,

WRH

is an input and indicates write transactions that access its internal

 

 

 

 

 

 

 

 

 

 

 

 

 

memory or universal registers.

 

ACK

I/O/T/OD

epu1

 

Acknowledge. External slave devices can deassert ACK to add wait states to external

 

 

 

 

 

 

 

 

 

 

(pu_od_0)

 

 

memory accesses. ACK is used by I/O devices, memory controllers, and other periph-

 

 

 

 

 

 

 

 

 

 

 

 

 

erals on the data phase. The DSP can deassert ACK to add wait states to read and write

 

 

 

 

 

 

 

 

 

 

 

 

 

accesses of its internal memory. The pull-up is 50 Ω on low-to-high transactions and

 

 

 

 

 

 

 

 

 

 

 

 

 

is 500 Ω on all other transactions.

 

 

 

 

 

 

 

O/T

na

 

Boot Memory Select.

 

 

 

 

 

 

 

is the chip select for boot EPROM or flash memory. During

 

 

BMS

 

BMS

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

reset, the DSP uses

BMS

 

as a strap pin (EBOOT) for EPROM boot mode. In a multipro-

 

 

 

 

 

 

 

 

 

 

 

 

 

cessor system, the DSP bus master drives

BMS.

For details, see Reset and Booting on

 

 

 

 

 

 

 

 

 

 

 

 

 

Page 9 and the EBOOT signal description in Table 16 on Page 20.

 

 

 

 

 

 

O/T

nc

 

Memory Select.

 

 

 

or

 

 

 

 

is asserted whenever the DSP accesses memory banks 0

 

 

MS1–0

 

MS0

MS1

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

or 1, respectively.

MS1–0

are decoded memory address pins that change concurrently

 

 

 

 

 

 

 

 

 

 

 

 

 

with ADDR pins. When ADDR31:27 = 0b00110,

MS0

is asserted. When ADDR31:27 =

 

 

 

 

 

 

 

 

 

 

 

 

 

0b00111,

MS1

is asserted. In multiprocessor systems, the master DSP drives

MS1–0.

 

 

 

 

 

 

 

O/T

nc

Memory Select Host.

 

 

is asserted whenever the DSP accesses the host address

 

 

MSH

MSH

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

space (ADDR31 = 0b1).

MSH

is a decoded memory address pin that changes concur-

 

 

 

 

 

 

 

 

 

 

 

 

 

rently with ADDR pins. In a multiprocessor system, the bus master DSP drives

MSH.

 

 

 

 

 

 

I/O/T

epu1

 

Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading

 

 

BRST

 

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

or writing data associated with consecutive addresses. A slave device can ignore

 

 

 

 

 

 

 

 

 

 

 

 

 

addresses after the first one and increment an internal address counter after each

 

 

 

 

 

 

 

 

 

 

 

 

 

transfer. For host-to-DSP burst accesses, the DSP increments the address automati-

 

 

 

 

 

 

 

 

 

 

 

 

 

cally while

 

is asserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRST

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

1This external pull-up may be omitted for the ID = 000 TigerSHARC processor.

Rev. C Page 13 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Clock General-Purpose Algorithm Benchmarks at 600 MHzBenchmark Speed Cycles FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu DSP Memory Program SequencerInterrupt Controller Flexible Instruction SetInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceHost Interface DMA ControllerMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Reset and Booting Timer and GENERAL-PURPOSE I/ONo Boot, Run from Memory Addresses Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITSignal Type Term Description Pin Definitions-Clocks and ResetSclk Ratio RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeDSP performs DMA transfers according to the DMA Pin Definitions-External Port DMA/FlybySample the data instead of the TigerSHARC MakesLdqm Pin Definitions-External Port Sdram ControllerHdqm SDA10Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerCONTROLIMP0 Pin Definitions-Link PortsCONTROLIMP1 DS1Driver Mode Pin Definitions-Power, Ground, and ReferenceDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsMaximum Duty Cycle for Input Transient Voltage Electrical CharacteristicsMaximum Duty VIN Max VIN Min Cycle2ESD Sensitivity Package InformationAbsolute Maximum Ratings Package Brand InformationAC Asynchronous Signal Specifications Timing SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Reference Clocks-System Clock Sclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap Pins DS2-0 Static Pins-Must Be ConstantJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Receive Electrical Characteristics Link Port Lvds Transmit Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Thermal Characteristics for 25 mm × 25 mm Package Thermal CharacteristicsEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0ACKO Sdcke SCLKRAT1L0DATI1N L0DATI3NID2 TDI TMR0E DS2 Enedreg TCKDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNBGA Data for Use with Surface Mount Design Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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