Analog Devices ADSP-TS201S DS2-0 Static Pins-Must Be Constant, Strap SYS 9, Strap Pins

Page 29

ADSP-TS201S

Table 29. AC Signal Specifications (Continued)

(All values in this table are in nanoseconds.)

Name

Description

SetupInput (Min)

HoldInput (Min)

OutputValid (Max)

OutputHold (Min)

OutputEnable (Min)

OutputDisable (Max)

Reference Clock

 

 

 

 

 

 

1

1

 

 

 

 

 

 

 

 

 

 

DS2–08

Static Pins—Must Be Constant

—

—

—

—

—

—

—

SCLKRAT2–08

Static Pins—Must Be Constant

—

—

—

—

—

—

—

ENEDREG

Static Pins—Must Be Connected to VSS

—

—

—

—

—

—

—

STRAP SYS9, 10

Strap Pins

1.5

0.5

—

—

—

—

SCLK

JTAG SYS11, 12

JTAG System Pins

+2.5

+10.0

+12.0

–1.0

—

—

TCK

1The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.

2For input specifications on FLAG3–0 pins, see Table 21.

3These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.

4 For additional requirement details, see Reset and Booting on Page 9.

5 RST_IN clock reference is the falling edge of SCLK.

6 TDO output clock reference is the falling edge of TCK.

7 Reference clock depends on function.

8 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.

9 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.

10Specifications applicable during reset only.

11JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0, L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP, L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0, L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0, SCLKRAT2–0, DS2–0, ENEDREG.

12JTAG system output timing clock reference is the falling edge of TCK.

REFERENCE

 

 

CLOCK

 

 

1.25V

tSCLK OR tTCK

 

INPUT

 

 

SIGNAL

 

 

 

1.25V

INPUT

 

SETUP

OUTPUT

 

 

SIGNAL

 

 

OUTPUT

1.25V

 

VALID

 

THREE-

 

 

STATE

 

 

OUTPUT

 

 

DISABLE

 

 

INPUT

HOLD

OUTPUT

HOLD

OUTPUT ENABLE

Figure 15. General AC Parameters Timing

Rev. C Page 29 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Clock General-Purpose Algorithm Benchmarks at 600 MHzBenchmark Speed Cycles FIR filter per real tap 83 nsDual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB DSP Memory Program SequencerInterrupt Controller Flexible Instruction SetInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceHost Interface DMA ControllerMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Reset and Booting Timer and GENERAL-PURPOSE I/ONo Boot, Run from Memory Addresses Link Ports LvdsDevelopment Tools Power DomainsFiltering Reference Voltage and Clocks Additional Information Evaluation KITSignal Type Term Description Pin Definitions-Clocks and ResetSclk Ratio RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeDSP performs DMA transfers according to the DMA Pin Definitions-External Port DMA/FlybySample the data instead of the TigerSHARC MakesLdqm Pin Definitions-External Port Sdram ControllerHdqm SDA10Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerCONTROLIMP0 Pin Definitions-Link PortsCONTROLIMP1 DS1Driver Mode Pin Definitions-Power, Ground, and ReferenceDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionPin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Sclkvref Operating ConditionsMaximum Duty Cycle for Input Transient Voltage Electrical CharacteristicsMaximum Duty VIN Max VIN Min Cycle2ESD Sensitivity Package InformationAbsolute Maximum Ratings Package Brand InformationAC Asynchronous Signal Specifications Timing SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Reference Clocks-System Clock Sclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap Pins DS2-0 Static Pins-Must Be ConstantJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Receive Electrical Characteristics Link Port Lvds Transmit Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Thermal Characteristics for 25 mm × 25 mm Package Thermal CharacteristicsEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0ACKO Sdcke SCLKRAT1L0DATI1N L0DATI3NID2 TDI TMR0E DS2 Enedreg TCKDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNBGA Data for Use with Surface Mount Design Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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