Analog Devices ADSP-TS201S specifications Test Conditions, Output Disable Time

Page 37

ADSP-TS201S

STRENGTH 5

 

88

 

 

 

 

 

 

 

 

77

IOL

 

 

 

 

 

 

 

66

 

 

 

 

 

 

 

 

55

 

 

 

 

 

 

 

)

44

 

 

 

 

 

 

 

(mA

 

 

 

 

VDD_IO = 2.63V, –40°C

33

 

 

 

 

T

22

 

 

VDD_IO = 2.5V, +25°C

 

 

 

EN

 

 

 

 

 

11

 

 

 

 

VDD_IO = 2.63V, –40°C

URR

 

 

 

 

0

VDD_IO = 2.38V, +105°C

 

 

 

 

INC

–11

 

 

VDD_IO = 2.5V, +25°C

 

 

P

–22

 

 

 

 

 

 

 

UT

 

 

 

 

 

 

 

–33

VDD_IO = 2.38V, +105°C

 

 

 

 

UTP

–44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

–55

 

 

 

 

 

 

 

 

–66

 

 

 

 

 

IOH

 

 

–77

 

 

 

 

 

 

 

–88

 

 

 

 

 

 

 

 

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

 

 

 

OUTPUT PIN VOLTAGE (V)

 

 

Figure 31. Typical Drive Currents at Strength 5

STRENGTH 6

 

100

 

 

 

 

 

 

 

 

90

IOL

 

 

 

 

 

 

 

80

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

)

60

 

 

 

 

 

 

 

50

 

 

 

 

 

 

 

(mA

 

 

 

 

VDD_IO = 2.63V, –40°C

40

 

 

 

 

T

30

 

 

VDD_IO = 2.5V, +25°C

 

 

REN

 

 

 

 

20

VDD_IO = 2.38V, +105°C

 

VDD_IO = 2.63V, –40°C

10

 

UR

 

0

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

N

–10

 

 

 

 

 

 

 

PI

–20

 

 

VDD_IO = 2.5V, +25°C

 

 

 

T

 

 

 

 

 

–30

 

 

 

 

 

 

 

TPU

VDD_IO = 2.38V, +105°C

 

 

 

 

–40

 

 

 

 

OU

–50

 

 

 

 

 

 

 

 

–60

 

 

 

 

 

 

 

 

–70

 

 

 

 

 

IOH

 

 

–80

 

 

 

 

 

 

 

–90

 

 

 

 

 

 

 

 

–100

 

 

 

 

 

 

 

 

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

 

 

 

OUTPUT PIN VOLTAGE (V)

 

 

Figure 32. Typical Drive Currents at Strength 6

STRENGTH 7

 

110

 

 

 

 

 

 

 

 

100

IOL

 

 

 

 

 

 

 

90

 

 

 

 

 

 

 

80

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

(mA)

60

 

 

 

 

VDD_IO = 2.63V, –40°C

50

 

 

 

 

40

 

 

 

 

 

 

 

RENT

 

 

VDD_IO = 2.5V, +25°C

 

 

 

30

 

 

 

 

 

20

 

 

 

VDD_IO = 2.63V, –40°C

 

CUR

10

VDD_IO = 2.38V, +105°C

 

0

 

 

 

 

PIN

–10

 

 

VDD_IO = 2.5V, +25°C

 

 

 

–20

 

 

 

 

 

UT

–30

 

 

 

 

 

 

 

UTP

–40

VDD_IO = 2.38V, +105°C

 

 

 

 

–50

 

 

 

 

O

–60

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–70

 

 

 

 

 

IOH

 

 

–80

 

 

 

 

 

 

 

–90

 

 

 

 

 

 

 

 

–100

 

 

 

 

 

 

 

 

–110

 

 

 

 

 

 

 

 

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

OUTPUT PIN VOLTAGE (V)

Figure 33. Typical Drive Currents at Strength 7

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in Table 29 on Page 28. These include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 34.

INPUT

 

 

OR

1.25V

1.25V

OUTPUT

Figure 34. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they stop driv- ing, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the fol- lowing equation:

tDECAY = (CLΔV) ⁄ IL

The output disable time tDIS is the difference between

tMEASURED_DIS and tDECAY as shown in Figure 35. The time

tMEASURED_DIS is the interval from when the reference signal switches to when the output voltage decays ΔV from the mea-

sured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with ΔV equal to 0.4 V.

REFERENCE

SIGNAL

tMEASURED_DIS

tMEASURED_ENA

tDIS

 

tENA

 

VOH (MEASURED)

 

 

 

 

VOH (MEASURED) – ￿V

1.65V

VOL (MEASURED)

VOL (MEASURED) + ￿V

0.85V

tDECAY

tRAMP

 

OUTPUT STOPS

OUTPUT STARTS

DRIVING

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.25V.

Figure 35. Output Enable/Disable

Rev. C Page 37 of 48 December 2006

Page 36 Page 38
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Page 36 Page 38
Contents ADSP-TS201S ADSP-TS201S Clock General-Purpose Algorithm Benchmarks at 600 MHzBenchmark Speed Cycles FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu DSP Memory Program SequencerInterrupt Controller Flexible Instruction SetInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceHost Interface DMA ControllerMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Reset and Booting Timer and GENERAL-PURPOSE I/ONo Boot, Run from Memory Addresses Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITSignal Type Term Description Pin Definitions-Clocks and ResetSclk Ratio RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeDSP performs DMA transfers according to the DMA Pin Definitions-External Port DMA/FlybySample the data instead of the TigerSHARC MakesLdqm Pin Definitions-External Port Sdram ControllerHdqm SDA10Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerCONTROLIMP0 Pin Definitions-Link PortsCONTROLIMP1 DS1Driver Mode Pin Definitions-Power, Ground, and ReferenceDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsMaximum Duty Cycle for Input Transient Voltage Electrical CharacteristicsMaximum Duty VIN Max VIN Min Cycle2ESD Sensitivity Package InformationAbsolute Maximum Ratings Package Brand InformationAC Asynchronous Signal Specifications Timing SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Reference Clocks-System Clock Sclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap Pins DS2-0 Static Pins-Must Be ConstantJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Receive Electrical Characteristics Link Port Lvds Transmit Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Thermal Characteristics for 25 mm × 25 mm Package Thermal CharacteristicsEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0ACKO Sdcke SCLKRAT1L0DATI1N L0DATI3NID2 TDI TMR0E DS2 Enedreg TCKDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNBGA Data for Use with Surface Mount Design Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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