Analog Devices ADSP-TS201S specifications Times Andfall Rise Fall Time

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						STRENGTH 4
						(VDD_IO = 2.5V)
	25
(ns)
TIMES	20
TIMES
ANDFALL	15
ANDFALL
RISE	10
RISE					FALL TIME
					Y = 0.0592x + 1.0629
	5
									RISE TIME
									Y = 0.0573x + 0.9789
	0	10	20	30	40	50	60	70	80	90	100
	0	10	20	30	40	50	60	70	80	90	100
				LOAD CAPACITANCE (pF)

Figure 41. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 4

						STRENGTH 5
						(VDD_IO = 2.5V)
	25
(ns)	20
TIMES	20
TIMES
FALLAND	15
	15
RISE	10
RISE					FALL TIME
					Y = 0.0493x + 0.8389
	5
									RISE TIME
	0							Y = 0.0481x + 0.7889
	0	10	20	30	40	50	60	70	80	90	100
	0	10	20	30	40	50	60	70	80	90	100
				LOAD CAPACITANCE (pF)

Figure 42. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 5


			STRENGTH 6

	25	(VDD_IO = 2.5V)
(ns)



TIMES	20
FALLAND	15
RISE	15
	10
							RISE	TIME

		FALL TIME					Y = 0.0377x + 0.7449
5
		Y = 0.0374x + 0.851

0	10	20	30	40	50	60	70	80	90	100
0
			LOAD CAPACITANCE (pF)

Figure 43. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 6

ADSP-TS201S


			STRENGTH 7
	25		(VDD_IO = 2.5V)
(ns)



TIMES	20
FALLAND	15
	15
RISE	10


							RISE TIME
							RISE TIME

		FALL TIME					Y = 0.0321x + 0.6512
5
		Y = 0.0313x + 0.818

0	10	20	30	40	50	60	70	80	90	100
0
			LOAD CAPACITANCE (pF)

Figure 44. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 7

	15				STRENGTH 0–7						0
						(VDD_IO = 2.5V)
(ns)	10
VALID											1
OUTPUT											1
											2
	5										3
											4


											5
											6
											7
	0
	0	10	20	30	40	50	60	70	80	90	100
				LOAD CAPACITANCE (pF)

Figure 45. Typical Output Valid (VDD_IO = 2.5 V) vs. Load Capacitance at Max Case Temperature and Strength 0 to 71

1The line equations for the output valid vs. load capacitance are: Strength 0: y = 0.1255x + 2.7873

Strength 1: y = 0.0764x + 1.0492

Strength 2: y = 0.0474x + 1.0806

Strength 3: y = 0.0345x + 1.2329

Strength 4: y = 0.0296x + 1.2064

Strength 5: y = 0.0246x + 1.0944

Strength 6: y = 0.0187x + 1.1005

Strength 7: y = 0.0156x + 1.084

Rev. C Page 39 of 48 December 2006

Image 39

Contents ADSP-TS201S ADSP-TS201S FIR filter per real tap 83 ns General-Purpose Algorithm Benchmarks at 600 MHzClock Benchmark Speed CyclesDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Flexible Instruction Set Program SequencerDSP Memory Interrupt ControllerInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceSdram Controller DMA ControllerHost Interface Multiprocessor InterfaceDMA controller provides these additional features Link Ports Lvds Timer and GENERAL-PURPOSE I/OReset and Booting No Boot, Run from Memory AddressesPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Additional Information Evaluation KITRatio Pin Definitions-Clocks and ResetSignal Type Term Description Sclk RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeMakes Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Sample the data instead of the TigerSHARCSDA10 Pin Definitions-External Port Sdram ControllerLdqm HdqmPin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerDS1 Pin Definitions-Link PortsCONTROLIMP0 CONTROLIMP1Impedance Control Selection Pin Definitions-Power, Ground, and ReferenceDriver Mode DS2-0 Drive Output Pins Strength ImpedancePin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Sclkvref Operating ConditionsVIN Max VIN Min Cycle2 Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage Maximum DutyPackage Brand Information Package InformationESD Sensitivity Absolute Maximum RatingsReference Clocks-Core Clock Cclk Cycle Time Timing SpecificationsAC Asynchronous Signal Specifications General AC TimingParameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap SYS 9 DS2-0 Static Pins-Must Be ConstantStrap Pins Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0VOD Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Parameter Condition Typical Unit Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Environmental ConditionsBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0DATI3N Sdcke SCLKRAT1L0ACKO L0DATI1NL1CLKINN DS2 Enedreg TCKID2 TDI TMR0E DS1 CONTROLIMP1 TDO FLAG3Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Surface Mount DesignBGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad SizeTemperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December