Analog Devices ADSP-TS201S specifications DMA controller provides these additional features

Page 8

ADSP-TS201S

 

ADSP-TS201S #7

 

 

 

 

 

ADSP-TS201S #6

 

 

 

 

 

ADSP-TS201S #5

CONTROL

ADDRESS

 

 

 

ADSP-TS201S #4

DATA

 

 

ADSP-TS201S #3

 

 

ADSP-TS201S #2

 

 

ADSP-TS201S #1

 

 

 

 

 

 

001

ID2–0

BR7–2,0

 

 

 

 

 

RST_IN

BR1

 

 

 

 

 

CLKS/REFS

ADDR31–0

 

 

 

 

 

DATA31–0

 

 

 

 

 

 

 

 

 

 

LINK

LINK

CONTROL

 

 

 

 

DEVICES

 

 

 

 

 

 

 

 

 

 

 

ADSP-TS201S #0

CONTROL

ADDRESS

DATA

 

000

ID2–0

BR7–1

 

 

 

BR0

 

RESET

RST_IN

ADDR31–0

 

 

ADDR

 

 

CLKS/REFS

DATA31–0

 

 

DATA

GLOBAL

 

RST_OUT

RD

 

 

OE

MEMORY

 

 

 

AND

 

POR_IN

 

 

 

 

WRL

 

 

WE

PERIPHERALS

CLOCK

SCLK

ACK

 

 

ACK

(OPTIONAL)

 

 

 

 

 

MS1–0

 

 

CS

 

 

 

BUSLOCK

 

 

 

 

 

 

BMS

 

 

CS

BOOT

 

 

CPA

 

 

ADDR

REFERENCE

SCLK_VREF

 

 

EPROM

REFERENCE

VREF

DPA

 

 

DATA

(OPTIONAL)

BRST

 

 

 

 

SCLKRAT2–0

 

 

 

 

 

DMAR3–0

 

 

 

CLOCK

 

 

BOFF

 

 

 

HOST

 

 

HBR

 

 

 

 

IRQ3–0

 

 

 

PROCESSOR

 

FLAG3–0

HBG

 

 

 

INTERFACE

 

MSH

 

 

 

(OPTIONAL)

 

 

 

 

 

 

LINK

 

 

 

 

 

IORD

 

 

ADDR

 

LxDATO3–0P/N

 

 

 

IOWR

 

 

 

 

 

LxCLKOUTP/N

 

 

DATA

 

 

IOEN

 

 

 

LINK

LxACKI

 

 

 

 

MSSD3–0

 

 

CS

 

DEVICES

LxBCMPO

 

 

SDRAM MEMORY

 

 

 

RAS

 

 

RAS

(2 MAX)

LxDATI3–0P/N

 

 

(OPTIONAL)

(OPTIONAL)

CAS

 

 

CAS

 

LxCLKINP/N

 

 

 

 

LDQM

 

 

DQM

 

 

LxACKO

 

 

 

 

 

 

 

 

 

LxBCMPI

 

 

SDWE

 

 

 

 

WE

 

TMR0E

 

 

SDCKE

 

 

 

 

 

 

 

 

 

 

 

CKE

 

BM

 

 

 

 

 

 

 

 

 

SDA10

 

 

 

 

 

A10

 

 

 

 

 

 

 

 

CONTROLIMP1–0

 

 

 

 

 

 

 

ADDR

 

CONTROL

 

 

 

 

 

 

 

 

 

DATA

CLK

 

 

 

 

 

 

DS2–0

JTAG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4. ADSP-TS201S Shared Memory Multiprocessing System

external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels.

•AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer.

The DMA controller provides these additional features:

•Flyby transfers. Flyby operations only occur through the external port (DMA Channel 0) and do not involve the DSP’s core. The DMA controller acts as a conduit to trans- fer data from an I/O device to external SDRAM memory.

During a transaction, the DSP relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0); outputs the IORD, IOWR, IOEN, and RD/WR strobes; and responds to ACK.

•DMA chaining. DMA chaining operations enable applica- tions to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes.

•Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions.

Rev. C Page 8 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 nsDual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceDMA Controller Host InterfaceMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports LvdsDevelopment Tools Power DomainsFiltering Reference Voltage and Clocks Evaluation KIT Additional InformationPin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationPin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC MakesPin Definitions-External Port Sdram Controller LdqmHdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionPin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionPin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Operating Conditions SclkvrefElectrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand InformationTiming Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxDS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsSdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3NDS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNSurface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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