Cypress CY7C67200 manual IN/OUT Ignore Enable Bit, Stall Enable Bit, NAK Interrupt Enable Bit

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CY7C67200

Figure 30. Device n Endpoint n Control Register

Bit #

15

14

13

12

 

11

10

9

8

Field

 

 

 

 

Reserved

 

 

 

Read/Write

-

-

-

-

 

-

-

-

-

Default

X

X

X

X

 

X

X

X

X

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

 

IN/OUT

Sequence

Stall

ISO

NAK

Direction

Enable

Arm

Field

Ignore

Select

Enable

Enable

Interrupt

Select

 

Enable

Enable

 

 

 

Enable

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

X

X

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

Register Description

The Device n Endpoint n Control register provides control over a single EP in device mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Control register.

IN/OUT Ignore Enable (Bit 6)

The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore all IN and OUT requests. This bit must be set so that EP0 only excepts Setup packets at the start of each transfer. This bit must be cleared to except IN/OUT transactions. This bit only applies to EP0.

1:Ignore IN/OUT requests

0:Do not ignore IN/OUT requests

Sequence Select (Bit 6)

The Sequence Select bit determines whether a DATA0 or a DATA1 will be sent for the next data toggle. This bit has no effect on receiving data packets, sequence checking must be handled in firmware.

1:Send a DATA1

0:Send a DATA0

Stall Enable (Bit 5)

The Stall Enable bit sends a Stall in response to the next request (unless it is a setup request, which are always ACKed). This is a sticky bit and continues to respond with Stalls until cleared by firmware.

1:Send Stall

0:Do not send Stall

ISO Enable (Bit 4)

The ISO Enable bit enables and disables an Isochronous transaction. This bit is only valid for EPs 1–7 and has no function for EP0.

1:Enable Isochronous transaction

0:Disable Isochronous transaction

NAK Interrupt Enable (Bit 3)

The NAK Interrupt Enable bit enables and disables the gener- ation of an Endpoint n interrupt when the device responds to the host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable register must also be set. When a NAK is sent to the host, the corresponding EP Interrupt Flag in the Device n Status register will be set. In addition, the NAK Flag in the Device n Endpoint n Status register will be set.

1:Enable NAK interrupt

0:Disable NAK interrupt

Direction Select (Bit 2)

The Direction Select bit needs to be set according to the expected direction of the next data stage in the next trans- action. If the data stage direction is different from what is set in this bit, it will get NAKed and either the IN Exception Flag or the OUT Exception Flag will be set in the Device n Endpoint n Status register. If a setup packet is received and the Direction Select bit is set incorrectly, the setup will be ACKed and the Set-up Status Flag will be set (refer to the setup bit of the Device n Endpoint n Status register for details).

1:OUT transfer (host to device)

0:IN transfer (device to host)

Enable (Bit 1)

The Enable bit must be set to allow transfers to the endpoint. If Enable is set to ‘0’ then all USB traffic to this endpoint is ignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs will automatically be returned from this endpoint (except setup packets, which are always ACKed as long as the Enable bit is set).

1:Enable transfers to an endpoint

0:Do not allow transfers to an endpoint

Arm Enable (Bit 0)

The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete.

1:Arm endpoint

0:Endpoint disarmed

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Contents Typical Applications EZ-OTG FeaturesCY7C67200 CY16Interface Descriptions IntroductionProcessor Core Functional Overview OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceSPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHost Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump InterfaceCrystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode PinSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 RCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHost/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitOTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitGpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitLock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe BitGeneral USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAPort a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnableSync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag BitHost n PID Register W ACK Flag BitPID Select Definition PID SelectHost n Device Address Register W Host n Count Result Register RID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/DeviceStall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WTimeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WSOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable BitEP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register WReceive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable BitSAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitSPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name AddressID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag BitDone1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name AddressPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init BitTransfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsTransmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WSPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name AddressScale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Uart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Name Type Pin DiagramPin Descriptions A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics Reset Timing AC Timing CharacteristicsParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Document History Issue Orig. Description of Change Date
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