Cypress CY7C67200 manual Host Port Interface HPI, HPI Interface Pins 1 Pin Name Pin Number

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CY7C67200

Host Port Interface (HPI)

EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plus a bidirectional mailbox register for supporting high-level communication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of EZ-OTG can be accomplished through this interface via an extensible API and communication protocol. Other than the hardware communication protocols, a host processor has identical control over EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.

Note It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs for a test mode. If these pins need to be used as inputs, a series resistor is required (10 ohm to 48 ohm is recom- mended). Refer to BIOS documentation for addition details. See section “Reset Pin” on page 9.

HPI Features

•16-bit data bus interface

•16 MB/s throughput

•Auto-increment of address pointer for fast block mode transfers

•Direct memory access (DMA) to internal memory

•Bidirectional Mailbox register

•Byte Swapping

•Complete access to internal memory

•Complete control of SIEs through HPI

•Dedicated HPI Status register

Table 9. HPI Interface Pins [1, 2]

(continued)

Pin Name

 

Pin Number

D7

 

B5

 

 

 

D6

 

B4

D5

 

C4

 

 

 

D4

 

B3

 

 

 

D3

 

A3

 

 

 

D2

 

C3

 

 

 

D1

 

A2

D0

 

B2

 

 

 

The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 10 below.

Table 10.HPI Addressing

HPI A[1:0]

A1

A0

HPI Data

0

0

HPI Mailbox

0

1

HPI Address

1

0

HPI Status

1

1

Charge Pump Interface

VBUS for the USB On-The-Go (OTG) port can be produced by EZ-OTG using its built-in charge pump and some external components. The circuit connections should look similar to Figure 1 below.

Figure 1. Charge Pump

HPI Pins

Table 9. HPI Interface Pins [1, 2]

Pin Name

Pin Number

INT

H4

 

 

nRD

G4

 

 

nWR

H5

 

 

nCS

G5

 

 

A1

H6

CSWITCHA

CY7C67200

CSWITCHB

OTGVBUS

D1D2

C1

VBUS

 

 

C2

A0

F5

D15

F6

 

 

D14

E4

 

 

D13

E5

 

 

D12

E6

 

 

D11

D4

 

 

D10

D5

 

 

D9

C6

 

 

D8

C5

Notes

1.HPI_INT is for the Outgoing Mailbox Interrupt.

2.HPI strobes are negative logic sampled on rising edge.

Component details:

•D1 and D2: Schottky diodes with a current rating greater than 60 mA.

•C1: Ceramic capacitor with a capacitance of 0.1 µF.

•C2: Capacitor value must be no more that 6.5 µF since that is the maximum capacitance allowed by the USB OTG specification for a dual-role device. The minimum value of C2 is 1 µF. There are no restrictions on the type of capacitor for C2.

If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon- nected.

Document #: 38-08014 Rev. *G

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Contents Typical Applications EZ-OTG FeaturesCY7C67200 CY16Interface Descriptions IntroductionProcessor Core Functional Overview OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceSPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHost Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump InterfaceCrystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode PinSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 RCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHost/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitOTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitGpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitLock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe BitGeneral USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAPort a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnableSync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag BitHost n PID Register W ACK Flag BitPID Select Definition PID SelectHost n Device Address Register W Host n Count Result Register RID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/DeviceStall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WTimeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WSOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable BitEP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register WReceive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable BitSAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitSPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name AddressID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag BitDone1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name AddressPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init BitTransfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsTransmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WSPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name AddressScale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Uart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Name Type Pin DiagramPin Descriptions A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics Reset Timing AC Timing CharacteristicsParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Document History Issue Orig. Description of Change Date
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