Cypress CY7C67200 Device n Interrupt Enable Register R/W, SOF/EOP Timeout Interrupt Enable Bit

Page 34

CY7C67200

Device n Interrupt Enable Register [R/W]

•Device 1 Interrupt Enable Register 0xC08C

•Device 2 Interrupt Enable Register 0xC0AC

Figure 35. Device n Interrupt Enable Register

Bit #

15

14

 

13

 

12

 

11

 

10

9

8

 

VBUS

ID Interrupt

 

Reserved

 

SOF/EOP

 

Reserved

SOF/EOP

Reset

Field

Interrupt

Enable

 

 

 

 

 

Timeout

 

 

Interrupt

Interrupt

Enable

 

 

 

 

 

 

Interrupt Enable

 

 

Enable

Enable

Read/Write

R/W

R/W

 

-

 

-

 

R/W

 

-

R/W

R/W

Default

0

0

 

0

 

0

 

0

 

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

 

5

 

4

 

3

2

1

0

Field

EP7 Interrupt

EP6 Interrupt

EP5 Interrupt

EP4 Interrupt

EP3 Interrupt

EP2 Interrupt

EP1 Interrupt

EP0 Interrupt

Enable

Enable

Enable

Enable

Enable

 

Enable

Enable

Enable

Read/Write

R/W

R/W

R/W

R/W

R/W

 

R/W

R/W

R/W

Default

0

0

 

0

 

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Description

The Device n Interrupt Enable register provides control over device-related interrupts including eight different endpoint interrupts.

VBUS Interrupt Enable (Bit 15)

The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2.

1:Enable VBUS interrupt

0:Disable VBUS interrupt

ID Interrupt Enable (Bit 14)

The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2.

1:Enable ID interrupt

0:Disable ID interrupt

SOF/EOP Timeout Interrupt Enable (Bit 11)

The SOF/EOP Timeout Interrupt Enable bit enables or disables the SOF/EOP Timeout Interrupt. When enabled this interrupt triggers when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP Count register. In addition, the Device n Frame register counts the number of times the SOF/EOP Timeout Interrupt triggers between receiving SOF/EOPs.

1:SOF/EOP timeout occurred

0:SOF/EOP timeout did not occur

SOF/EOP Interrupt Enable (Bit 9)

The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP received interrupt.

1:Enable SOF/EOP Received interrupt

0:Disable SOF/EOP Received interrupt

Reset Interrupt Enable (Bit 8)

The Reset Interrupt Enable bit enables or disables the USB Reset Detected interrupt

1:Enable USB Reset Detected interrupt

0:Disable USB Reset Detected interrupt

EP7 Interrupt Enable (Bit 7)

The EP7 Interrupt Enable bit enables or disables an endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt.

1:Enable EP7 Transaction Done interrupt

0:Disable EP7 Transaction Done interrupt

EP6 Interrupt Enable (Bit 6)

The EP6 Interrupt Enable bit enables or disables an endpoint six (EP6) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt.

1:Enable EP6 Transaction Done interrupt

0:Disable EP6 Transaction Done interrupt

Document #: 38-08014 Rev. *G

Page 34 of 78

[+] Feedback

Page 33 Page 35
Image 34
Page 33 Page 35
Contents CY7C67200 EZ-OTG FeaturesTypical Applications CY16Processor Core Functional Overview IntroductionInterface Descriptions USB Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number OTG InterfaceHSS Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Addressing HPI A10 HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI Charge Pump InterfaceBooster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Boot Mode Crystal Pins Pin Name Pin NumberBoot Configuration Interface PinPower Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Reserved Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedOTG Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit HSS Wake Enable BitSPI Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit Host/Device 2 Interrupt Enable BitTimer 1 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 0 Interrupt Enable BitPull-down Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit LS Pull-up Enable BitWDT Enable Bit Timeout Flag BitLock Enable Bit Reset Strobe BitUSB Registers Register Name Address SIE1/SIE2 Timer n Register R/WGeneral USB Registers 0xC08A/0xC0AAUSB Data Line Pull-up and Pull-down Resistors Mode Port n Mode Select BitPort a Resistors Enable Bit Resistors Function Select EnableISO Enable Bit Preamble Enable BitSync Enable Bit Arm Enable BitHost n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Stall Flag Bit Error Flag BitUnderflow Flag Bit NAK Flag BitPID Select Definition ACK Flag BitHost n PID Register W PID SelectHost n Count Result Register R Host n Device Address Register WSOF/EOP Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit Port a Wake Interrupt Enable BitSOF/EOP Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit Port a Wake Interrupt Flag BitCount Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R USB Device Only Registers Host n Frame Register RUSB Device Only Registers Reserved Register Name Address Device 1/DeviceNAK Interrupt Enable Bit IN/OUT Ignore Enable BitStall Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitError occurred Error did not occur Setup Flag BitTimeout occurred Timeout condition did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterReset Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit EP7 Interrupt Enable BitEP3 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitDevice n Frame Number Register R SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n SOF/EOP Count Register WCharge Pump Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Vbus Discharge Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Write Protect Enable BitSAS Enable Bit Vbus Valid Flag BitInterrupt 0 Enable Bit HSS Enable BitSPI Enable Bit Interrupt 0 Polarity Select BitGpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit RTS Polarity Select BitReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Packet Ready Flag BitTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHPI Registers HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers Register Name AddressSOF/EOP2 to HPI Enable Bit Vbus to HPI Enable BitID to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to CPU Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit Reset2 to HPI Enable BitData Bits SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WID Flag Bit Reset2 Flag BitVbus Flag Bit SOF/EOP2 Flag BitMailbox Out Flag Bit SPI Registers Reset1 Flag BitDone1 Flag Bit SPI Registers Register Name AddressMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit Fifo Init BitFifo Error Flag Bit Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Receive Bit Length BitsTransfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transmit Interrupt Clear BitReceive CRC Bit CRC Enable BitCRC Clear Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WUart Registers SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Register Name AddressBaud Select Bits Uart Enable BitScale Select Bit Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Descriptions Pin DiagramPin Descriptions Name Type GPIO19 General Purpose IO GPIO20 General Purpose IOA1 HPI A1 A0 HPI A0Operating Conditions Booster Power Input 2.7V toAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingI2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Pulse Width Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time Document # 38-08014 Rev. *GHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Ordering Code Package Type PB-Free Package DiagramOrdering Information Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History
Top Page Image Contents