Cypress CY7C67200 3Wire Enable Bit, Phase Select Bit, SCK Polarity Select Bit, Scale Select Bits

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CY7C67200

3Wire Enable (Bit 15)

The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation.

1:MISO and MOSI data lines are tied together

0:Normal MISO and MOSI Full Duplex operation (not tied together)

Phase Select (Bit 14)

The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode.

1:Advanced SCK phase

0:Delayed SCK phase

SCK Polarity Select (Bit 13)

This SCK Polarity Select bit selects the polarity of SCK.

1:Positive SCK polarity

0:Negative SCK polarity

Scale Select (Bits [12:9])

The Scale Select field provides control over the SCK frequency, based on 48 MHz. See Table 34 for a definition of this field. This field only applies to master mode.

Table 34.Scale Select Field Definition for SCK Frequency

Scale Select [12:9]	SCK Frequency
0000	12 MHz
0001	8 MHz
0010	6 MHz
0011	4 MHz
0100	3 MHz
0101	2 MHz
0110	1.5 MHz
0111	1 MHz
1000	750 KHz
1001	500 KHz
1010	375 KHz
1011	250 KHz
1100	375 KHz
1101	250 KHz
1110	375 KHz
1111	250 KHz

Master Active Enable (Bit 7)

The Master Active Enable bit is a read-only bit that indicates if the master state machine is active or idle. This field only applies to master mode.

1:Master state machine is active

0:Master state machine is idle

Master Enable (Bit 6)

The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads ‘0’, otherwise value will not change.

1:Master SPI interface

0:Slave SPI interface

SS Enable (Bit 5)

The SS Enable bit enables or disables the master SS output.

1:Enable master SS output

0:Disable master SS output (three-state master SS output, for single SS line in slave mode)

SS Delay Select (Bits [4:0])

When the SS Delay Select field is set to ‘00000’ this indicates manual mode. In manual mode SS is controlled by the SS Manual bit of the SPI Control register. When the SS Delay Select field is set between ‘00001’ to ‘11111’, this value indicates the count in half bit times of auto transfer delay for:

SSLOW to SCK active, SCK inactive to SS HIGH, SS HIGH time. This field only applies to master mode.

Document #: 38-08014 Rev. *G

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Contents CY7C67200 EZ-OTG FeaturesTypical Applications CY16Introduction Processor Core Functional OverviewInterface Descriptions USB Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number OTG InterfaceHSS Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Addressing HPI A10 HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI Charge Pump InterfaceCharge Pump Interface Pins Pin Name Pin Number Booster InterfaceCrystal Interface Boot Mode Crystal Pins Pin Name Pin NumberBoot Configuration Interface PinPower Savings and Reset Description Power Savings Mode DescriptionSleep Memory Map Registers Reserved Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedOTG Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit HSS Wake Enable BitSPI Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit Host/Device 2 Interrupt Enable BitTimer 1 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 0 Interrupt Enable BitPull-down Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit LS Pull-up Enable BitWDT Enable Bit Timeout Flag BitLock Enable Bit Reset Strobe BitUSB Registers Register Name Address SIE1/SIE2 Timer n Register R/WGeneral USB Registers 0xC08A/0xC0AAUSB Data Line Pull-up and Pull-down Resistors Mode Port n Mode Select BitPort a Resistors Enable Bit Resistors Function Select EnableISO Enable Bit Preamble Enable BitSync Enable Bit Arm Enable BitHost n Address Register R/W Host n Count Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Stall Flag Bit Error Flag BitUnderflow Flag Bit NAK Flag BitPID Select Definition ACK Flag BitHost n PID Register W PID SelectHost n Count Result Register R Host n Device Address Register WSOF/EOP Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit Port a Wake Interrupt Enable BitSOF/EOP Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Count Register R/W Count Bits Count field sets the SOF/EOP counter durationHost n SOF/EOP Counter Register R USB Device Only Registers Host n Frame Register RUSB Device Only Registers Reserved Register Name Address Device 1/DeviceNAK Interrupt Enable Bit IN/OUT Ignore Enable BitStall Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitError occurred Error did not occur Setup Flag BitTimeout occurred Timeout condition did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterReset Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit EP7 Interrupt Enable BitEP3 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitDevice n Frame Number Register R SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n SOF/EOP Count Register WCharge Pump Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Vbus Discharge Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Write Protect Enable BitSAS Enable Bit Vbus Valid Flag BitInterrupt 0 Enable Bit HSS Enable BitSPI Enable Bit Interrupt 0 Polarity Select BitGpio 0 Input Data Register 0xC020 R Gpio 1 Input Data Register 0xC026 RGpio 0 Direction Register 0xC022 R/W Gpio 1 Direction Register 0xC028 R/W HSS RegistersHSS Registers Register Name Address Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit RTS Polarity Select BitReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Packet Ready Flag BitHSS Transmit Gap Register 0xC074 R/W Transmit Gap Select BitsHSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHPI Registers HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers Register Name AddressSOF/EOP2 to HPI Enable Bit Vbus to HPI Enable BitID to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to CPU Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit Reset2 to HPI Enable BitData Bits SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WID Flag Bit Reset2 Flag BitVbus Flag Bit SOF/EOP2 Flag BitMailbox Out Flag Bit SPI Registers Reset1 Flag BitDone1 Flag Bit SPI Registers Register Name AddressMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit Fifo Init BitFifo Error Flag Bit Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Receive Bit Length BitsTransfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transmit Interrupt Clear BitReceive CRC Bit CRC Enable BitCRC Clear Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WUart Registers SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Register Name AddressBaud Select Bits Uart Enable BitScale Select Bit Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Diagram Pin DescriptionsPin Descriptions Name Type GPIO19 General Purpose IO GPIO20 General Purpose IOA1 HPI A1 A0 HPI A0Operating Conditions Booster Power Input 2.7V toAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingClock Timing I2C Eeprom TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Pulse Width Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time Document # 38-08014 Rev. *GHSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Ordering Code Package Type PB-Free Package DiagramOrdering Information Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History