Cypress CY7C67200 Vbus Interrupt Enable Bit, ID Interrupt Enable Bit, Done Interrupt Enable Bit

Page 25

CY7C67200

Host n Interrupt Enable Register [R/W]

•Host 1 Interrupt Enable Register 0xC08C

•Host 2 Interrupt Enable Register 0xC0AC

Figure 25. Host n Interrupt Enable Register

Bit #

15

14

13

12

 

11

10

9

8

Field

VBUS

ID Interrupt

 

 

Reserved

 

SOF/EOP

Reserved

Interrupt Enable

Enable

 

 

 

 

 

Interrupt Enable

 

Read/Write

R/W

R/W

-

-

 

-

-

R/W

-

Default

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

 

Reserved

Port A

Reserved

Port A Connect

 

Reserved

 

Done

Field

 

Wake Interrupt Enable

 

Change

 

 

 

Interrupt Enable

 

 

 

Interrupt Enable

 

 

 

 

Read/Write

-

R/W

-

R/W

-

-

-

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

Register Description

The Host n Interrupt Enable register allows control over host-related interrupts.

In this register a bit set to ‘1’ enables the corresponding interrupt while ‘0’ disables the interrupt.

VBUS Interrupt Enable (Bit 15)

The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.

1:Enable VBUS interrupt

0:Disable VBUS interrupt

ID Interrupt Enable (Bit 14)

The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.

1:Enable ID interrupt

0:Disable ID interrupt

SOF/EOP Interrupt Enable (Bit 9)

The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt.

1:Enable SOF/EOP timer interrupt

0:Disable SOF/EOP timer interrupt

Port A Wake Interrupt Enable (Bit 6)

The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A.

1:Enable remote wakeup interrupt for Port A

0:Disable remote wakeup interrupt for Port A

Port A Connect Change Interrupt Enable (Bit 4)

The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).

1:Enable Connect Change interrupt

0:Disable Connect Change interrupt

Done Interrupt Enable (Bit 0)

The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B.

1:Enable USB Transfer Done interrupt

0:Disable USB Transfer Done interrupt

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Contents Typical Applications EZ-OTG FeaturesCY7C67200 CY16Processor Core Functional Overview IntroductionInterface Descriptions OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceSPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHost Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump InterfaceBooster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode PinPower Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 RCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHost/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitOTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitGpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitLock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe BitGeneral USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAPort a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnableSync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable BitHost n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag BitHost n PID Register W ACK Flag BitPID Select Definition PID SelectHost n Device Address Register W Host n Count Result Register RID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitCount Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/DeviceStall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WTimeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WSOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable BitEP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register WReceive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable BitSAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitSPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag BitTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name AddressID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag BitDone1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name AddressPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init BitTransfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsTransmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WSPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name AddressScale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Uart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Pin DiagramPin Descriptions Name Type A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics Reset Timing AC Timing CharacteristicsI2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Document History Issue Orig. Description of Change Date
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