Cypress CY7C67200 OTG Control Registers, OTG Registers Register Name Address OTG Control Register

Page 39

CY7C67200

OTG Control Registers

There is one register dedicated for OTG operation. This register is covered in this section and summarized in Table 28.

OTG Control Register [0xC098] [R/W]

Table 28.OTG Registers

Register Name

Address

R/W

OTG Control Register

C098H

R/W

 

 

 

Figure 40. OTG Control Register

Bit #

15

14

13

12

11

10

9

8

Field

Reserved

VBUS

Receive

Charge Pump

VBUS

D+

D–

 

 

 

Pull-up

Disable

Enable

Discharge

Pull-up

Pull-up

 

 

 

Enable

 

 

Enable

Enable

Enable

Read/Write

-

-

R/W

R/W

R/W

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

Field

D+

D–

 

Reserved

 

OTG Data

ID

VBUS Valid

 

Pull-down

Pull-down

 

 

 

Status

Status

Flag

 

Enable

Enable

 

 

 

 

 

 

Read/Write

R/W

R/W

-

-

-

R

R

R

Default

0

0

0

0

0

X

X

X

 

 

 

 

 

 

 

 

 

Register Description

The OTG Control register allows control and monitoring over the OTG port on Port1A.

VBUS Pull-up Enable (Bit 13)

The VBUS Pull-up Enable bit enables or disables a 500 ohm pull-up resistor onto OTG VBus.

1:500 ohm pull-up resistor enabled

0:500 ohm pull-up resistor disabled

Receive Disable (Bit 12)

The Receive Disable bit enables or powers down (disables) the OTG receiver section.

1:OTG receiver powered down and disabled

0:OTG receiver enabled

Charge Pump Enable (Bit 11)

The Charge Pump Enable bit enables or disables the OTG VBus charge pump.

1:OTG VBus charge pump enabled

0:OTG VBus charge pump disabled

VBUS Discharge Enable (Bit 10)

The VBUS Discharge Enable bit enables or disables a 2K-ohm discharge pull-down resistor onto OTG VBus.

1:2K-ohm pull-down resistor enabled

0:2K-ohm pull-down resistor disabled

D+ Pull-up Enable (Bit 9)

The D+ Pull-up Enable bit enables or disables a pull-up resistor on the OTG D+ data line.

1:OTG D+ dataline pull-up resistor enabled

0:OTG D+ dataline pull-up resistor disabled

D– Pull-up Enable (Bit 8)

The D– Pull-up Enable bit enables or disables a pull-up resistor on the OTG D– data line.

1:OTG D– dataline pull-up resistor enabled

0:OTG D– dataline pull-up resistor disabled

D+ Pull-down Enable (Bit 7)

The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line.

1:OTG D+ dataline pull-down resistor enabled

0:OTG D+ dataline pull-down resistor disabled

D– Pull-down Enable (Bit 6)

The D– Pull-down Enable bit enables or disables a pull-down resistor on the OTG D– data line.

1:OTG D– dataline pull-down resistor enabled

0:OTG D– dataline pull-down resistor disabled

OTG Data Status (Bit 2)

The OTG Data Status bit is a read only bit and indicates the TTL logic state of the OTG VBus pin.

1:OTG VBus is greater than 2.4V

0:OTG VBus is less than 0.8V

ID Status (Bit 1)

The ID Status bit is a read only bit that indicates the state of the OTG ID pin on Port A.

1:OTG ID Pin is not connected directly to ground (>10K ohm)

0:OTG ID Pin is connected directly ground (< 10 ohm)

Document #: 38-08014 Rev. *G

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Contents CY16 EZ-OTG FeaturesTypical Applications CY7C67200Introduction Processor Core Functional OverviewInterface Descriptions OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number USB InterfaceSerial Peripheral Interface I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number HSS Interface Pins Pin Name Pin NumberCharge Pump Interface HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI HPI Addressing HPI A10Charge Pump Interface Pins Pin Name Pin Number Booster InterfaceCrystal Interface Pin Crystal Pins Pin Name Pin NumberBoot Configuration Interface Boot ModePower Savings and Reset Description Power Savings Mode DescriptionSleep Memory Map Registers Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHSS Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit OTG Wake Enable BitHost/Device 2 Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitTimer 0 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 1 Interrupt Enable BitLS Pull-up Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit Pull-down Enable BitReset Strobe Bit Timeout Flag BitLock Enable Bit WDT Enable Bit0xC08A/0xC0AA Timer n Register R/WGeneral USB Registers USB Registers Register Name Address SIE1/SIE2Resistors Function Select Enable Mode Select BitPort a Resistors Enable Bit USB Data Line Pull-up and Pull-down Resistors Mode Port nArm Enable Bit Preamble Enable BitSync Enable Bit ISO Enable BitHost n Address Register R/W Host n Count Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 NAK Flag Bit Error Flag BitUnderflow Flag Bit Stall Flag BitPID Select ACK Flag BitHost n PID Register W PID Select DefinitionHost n Device Address Register W Host n Count Result Register RPort a Wake Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit SOF/EOP Interrupt Flag BitHost n SOF/EOP Count Register R/W Count Bits Count field sets the SOF/EOP counter durationHost n SOF/EOP Counter Register R Register Name Address Device 1/Device Host n Frame Register RUSB Device Only Registers Reserved USB Device Only RegistersEnable Bit IN/OUT Ignore Enable BitStall Enable Bit NAK Interrupt Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WException Flag Bit Setup Flag BitTimeout occurred Timeout condition did not occur Error occurred Error did not occurDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WEP7 Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP1 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP3 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitDevice n SOF/EOP Count Register W SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n Frame Number Register RVbus Discharge Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Charge Pump Enable BitVbus Valid Flag Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 111 ReservedInterrupt 0 Polarity Select Bit HSS Enable BitSPI Enable Bit Interrupt 0 Enable BitGpio 0 Input Data Register 0xC020 R Gpio 1 Input Data Register 0xC026 RGpio 0 Direction Register 0xC022 R/W Gpio 1 Direction Register 0xC028 R/W HSS RegistersHSS Registers Register Name Address RTS Polarity Select Bit Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitReceive Packet Ready Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitHSS Transmit Gap Register 0xC074 R/W Transmit Gap Select BitsHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHPI Registers Register Name Address HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI RegistersHPI Breakpoint Register 0x0140 R Vbus to HPI Enable BitID to HPI Enable Bit SOF/EOP2 to HPI Enable BitReset2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit SOF/EOP1 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register Data BitsSOF/EOP2 Flag Bit Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Register Name Address SPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitFifo Init Bit Byte Mode BitRead Enable Bit SCK Strobe BitReceive Bit Length Bits Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Clear Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transfer Interrupt Flag BitOne in CRC Bit CRC Enable BitCRC Clear Bit Receive CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WUart Registers Register Name Address SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart RegistersUart Baud Select Definition Baud Rate DIV8 = Uart Enable BitScale Select Bit Baud Select BitsUart Data Register 0xC0E4 R/W Transmit Full BitPin Diagram Pin DescriptionsPin Descriptions Name Type A0 HPI A0 GPIO20 General Purpose IOA1 HPI A1 GPIO19 General Purpose IOCrystal Requirements XTALIN, Xtalout Booster Power Input 2.7V toAbsolute Maximum Ratings Operating ConditionsDC Characteristics Reset Timing AC Timing CharacteristicsClock Timing I2C Eeprom TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthHSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Package DiagramOrdering Information Ordering Information Ordering Code Package Type PB-FreeDocument History Issue Orig. Description of Change Date
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