Cypress CY7C67200 Port a D+ Status Bit, Port a D- Status Bit, Mode Select Bit, Suspend Enable Bit

Page 19

CY7C67200

Port A D+ Status (Bit 13)

The Port A D+ Status bit is a read-only bit that indicates the value of DATA+ on Port A.

1:D+ is high

0:D+ is low

Port A D– Status (Bit 12)

The Port A D– Status bit is a read-only bit that indicates the value of DATA– on Port A.

1:D– is high

0:D– is low

LOA (Bit 10)

The LOA bit selects the speed of Port A.

1:Port A is set to Low-speed mode

0:Port A is set to Full-speed mode

Mode Select (Bit 9)

The Mode Select bit sets the SIE for host or device operation. When set for device operation only one USB port is supported. The active port is selected by the Port Select bit in the Host n Count Register.

1:Host mode

0:Device mode

Port A Resistors Enable (Bit 7)

The Port A Resistors Enable bit enables or disables the pull-up/pull-down resistors on Port A. When enabled, the Mode Select bit and LOA bit of this register sets the pull-up/pull-down resistors appropriately. When the Mode Select is set for Host mode, the pull-down resistors on the data lines (D+ and D–) are enabled. When the Mode Select is set for Device mode, a single pull-up resistor on either D+ or D–, determined by the LOA bit, will be enabled. See Table 23 for details.

1:Enable pull-up/pull-down resistors

0:Disable pull-up/pull-down resistors

Table 23.USB Data Line Pull-up and Pull-down Resistors

 

Mode

Port n

 

L0A

Resistors

Function

Select

 

Enable

 

 

 

 

X

X

0

Pull up/Pull down on D+ and

 

 

 

D– Disabled

X

1

1

Pull down on D+ and D–

 

 

 

Enabled

1

0

1

Pull up on USB D– Enabled

 

 

 

 

0

0

1

Pull up on USB D+ Enabled

 

 

 

 

Port A Force D± State (Bits [4:3])

The Port A Force D± State field controls the forcing state of the D+ D– data lines for Port A. This field forces the state of the Port A data lines independent of the Port Select bit setting. See Table 24 for details.

Table 24.Port A Force D± State

Port A Force D± State

Function

MSB

LSB

 

0

0

Normal Operation

 

 

 

0

1

Force USB Reset, SE0 State

 

 

 

1

0

Force J-State

 

 

 

1

1

Force K-State

 

 

 

Suspend Enable (Bit 2)

The Suspend Enable bit enables or disables the suspend feature on both ports. When suspend is enabled the USB transceivers are powered down and can not transmit or received USB packets but can still monitor for a wakeup condition.

1:Enable suspend

0:Disable suspend

Port A SOF/EOP Enable (Bit 0)

The Port A SOF/EOP Enable bit is only applicable in host mode. In Device mode this bit must be written as ‘0’. In host mode this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs will be generated depending on the LOA bit in the USB n Control Register when Port A is active.

1:Enable SOFs or EOPs

0:Disable SOFs or EOPs

Reserved

All reserved bits must be written as ‘0’.

USB Host Only Registers

There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unless otherwise noted); one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summa- rized in Table 25.

Table 25.USB Host Only Register

Register Name

Address

R/W

(Host 1/Host 2)

 

 

Host n Control Register

0xC080/0xC0A0

R/W

 

 

 

Host n Address Register

0xC082/0xC0A2

R/W

 

 

 

Host n Count Register

0xC084/0xC0A4

R/W

 

 

 

Host n Endpoint Status Register

0xC086/0xC0A6

R

 

 

 

Host n PID Register

0xC086/0xC0A6

W

 

 

 

Host n Count Result Register

0xC088/0xC0A8

R

 

 

 

Host n Device Address Register

0xC088/0xC0A8

W

 

 

 

Host n Interrupt Enable Register

0xC08C/0xC0AC

R/W

 

 

 

Host n Status Register

0xC090/0xC0B0

R/W

 

 

 

Host n SOF/EOP Count Register

0xC092/0xC0B2

R/W

 

 

 

Host n SOF/EOP Counter

0xC094/0xC0B4

R

Register

 

 

Host n Frame Register

0xC096/0xC0B6

R

 

 

 

Document #: 38-08014 Rev. *G

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Contents CY16 EZ-OTG FeaturesTypical Applications CY7C67200Processor Core Functional Overview IntroductionInterface Descriptions OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number USB InterfaceSerial Peripheral Interface I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number HSS Interface Pins Pin Name Pin NumberCharge Pump Interface HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI HPI Addressing HPI A10Booster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Pin Crystal Pins Pin Name Pin NumberBoot Configuration Interface Boot ModePower Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHSS Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit OTG Wake Enable BitHost/Device 2 Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitTimer 0 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 1 Interrupt Enable BitLS Pull-up Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit Pull-down Enable BitReset Strobe Bit Timeout Flag BitLock Enable Bit WDT Enable Bit0xC08A/0xC0AA Timer n Register R/WGeneral USB Registers USB Registers Register Name Address SIE1/SIE2Resistors Function Select Enable Mode Select BitPort a Resistors Enable Bit USB Data Line Pull-up and Pull-down Resistors Mode Port nArm Enable Bit Preamble Enable BitSync Enable Bit ISO Enable BitHost n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 NAK Flag Bit Error Flag BitUnderflow Flag Bit Stall Flag BitPID Select ACK Flag BitHost n PID Register W PID Select DefinitionHost n Device Address Register W Host n Count Result Register RPort a Wake Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit SOF/EOP Interrupt Flag BitCount Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R Register Name Address Device 1/Device Host n Frame Register RUSB Device Only Registers Reserved USB Device Only RegistersEnable Bit IN/OUT Ignore Enable BitStall Enable Bit NAK Interrupt Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WException Flag Bit Setup Flag BitTimeout occurred Timeout condition did not occur Error occurred Error did not occurDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WEP7 Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP1 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP3 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitDevice n SOF/EOP Count Register W SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n Frame Number Register RVbus Discharge Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Charge Pump Enable BitVbus Valid Flag Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 111 ReservedInterrupt 0 Polarity Select Bit HSS Enable BitSPI Enable Bit Interrupt 0 Enable BitGpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address RTS Polarity Select Bit Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitReceive Packet Ready Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHPI Registers Register Name Address HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI RegistersHPI Breakpoint Register 0x0140 R Vbus to HPI Enable BitID to HPI Enable Bit SOF/EOP2 to HPI Enable BitReset2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit SOF/EOP1 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register Data BitsSOF/EOP2 Flag Bit Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Register Name Address SPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitFifo Init Bit Byte Mode BitRead Enable Bit SCK Strobe BitReceive Bit Length Bits Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Clear Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transfer Interrupt Flag BitOne in CRC Bit CRC Enable BitCRC Clear Bit Receive CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WUart Registers Register Name Address SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart RegistersUart Baud Select Definition Baud Rate DIV8 = Uart Enable BitScale Select Bit Baud Select BitsUart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Pin DiagramPin Descriptions Name Type A0 HPI A0 GPIO20 General Purpose IOA1 HPI A1 GPIO19 General Purpose IOCrystal Requirements XTALIN, Xtalout Booster Power Input 2.7V toAbsolute Maximum Ratings Operating ConditionsDC Characteristics Reset Timing AC Timing CharacteristicsI2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Package DiagramOrdering Information Ordering Information Ordering Code Package Type PB-FreeDocument History Issue Orig. Description of Change Date
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