Cypress CY7C67200 manual Memory Map

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CY7C67200

External (Remote) Wakeup Source

There are several possible events available to wake EZ-OTG from Sleep mode as shown in Table 15. These may also be used as remote wakeup options for USB applications. See section “Power Control Register [0xC00A] [R/W]” on page 13.

Upon wakeup, code begins executing within 200 ms, the time it takes the PLL to stabilize.

Table 15.wakeup Sources[3, 4]

Wakeup Source (if enabled)

Event

USB Resume

D+/D– Signaling

registers, USB control registers, the stack, and other BIOS variables. The upper internal memory space contains EZ-OTG control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to 0xFFFF. For more information on the reserved lower memory or the BIOS ROM, refer to the Programmers documentation and the BIOS documentation.

During development with the EZ-OTG toolset, the lower area of User's space (0x04A4 to 0x1000) should be left available to load the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-OTG.

Figure 6. Memory Map

OTGVBUS

Level

OTGID

Any Edge

 

 

HPI

Read

 

 

HSS

Read

 

 

SPI

Read

 

 

IRQ0 (GPIO 24)

Any Edge

Power-On Reset (POR) Description

The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal start up). A typical application might utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respec- tively.

Reset Pin

The Reset pin is active low and requires a minimum pulse duration of sixteen 12-MHz clock cycles (1.3 ms). A reset event restores all registers to their default POR settings. Code execution then begins 200 ms later at 0xFF00 with an imme- diate jump to 0xE000, the start of BIOS.

Note It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as out- puts for a test mode. If these pins need to be used as inputs, a series resistor is required (10 ohm to 48 ohm is recommend- ed). Refer to BIOS documentation for addition details.

USB Reset

A USB Reset affects registers 0xC090 and 0xC0B0, all other registers remain unchanged.

Memory Map

Memory map information is presented in this section.

Mapping

0x0000 - 0x00FF

0x0100 - 0x011F

0x0120 - 0x013F

0x0140 - 0x0148 0x014A - 0x01FF

0x0200- 0x02FF

0x0300- 0x030F

0x0310- 0x03FF

0x0400- 0x04A2

0x04A4- 0x3FFF

Internal Memory

HW INTs

SW INTs

Primary Registers

Swap Registers

HPI Int / Mailbox

LCP Variables

USB Registers

Slave Setup Packet

BIOS Stack

USB Slave & OTG

USER SPACE

~15K

The EZ-OTG has just over 24 KB of addressable memory mapped from 0x0000 to 0xFFFF. This 24 KB contains both program and data space and is byte addressable. Figure 6. shows the various memory region address locations.

Internal Memory

Of the internal memory, 15 KB is allocated for user’s program and data code. The lower memory space from 0x0000 to 0x04A2 is reserved for interrupt vectors, general purpose

Notes

3.Read data will be discarded (dummy data).

4.HPI_INT will assert on a USB Resume.registers

0xC000- 0xC0FF

Control Registers

0xE000- 0xFFFF

BIOS

Document #: 38-08014 Rev. *G

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Contents Typical Applications EZ-OTG FeaturesCY7C67200 CY16Introduction Processor Core Functional OverviewInterface Descriptions OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceSPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHost Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump InterfaceCharge Pump Interface Pins Pin Name Pin Number Booster InterfaceCrystal Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode PinPower Savings and Reset Description Power Savings Mode DescriptionSleep Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 RCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHost/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitOTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitGpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitLock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe BitGeneral USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAPort a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnableSync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable BitHost n Address Register R/W Host n Count Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag BitHost n PID Register W ACK Flag BitPID Select Definition PID SelectHost n Device Address Register W Host n Count Result Register RID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Count Register R/W Count Bits Count field sets the SOF/EOP counter durationHost n SOF/EOP Counter Register R USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/DeviceStall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WTimeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WSOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable BitEP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register WReceive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable BitSAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitSPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 0 Input Data Register 0xC020 R Gpio 1 Input Data Register 0xC026 RGpio 0 Direction Register 0xC022 R/W Gpio 1 Direction Register 0xC028 R/W HSS RegistersHSS Registers Register Name Address CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag BitHSS Transmit Gap Register 0xC074 R/W Transmit Gap Select BitsHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name AddressID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag BitDone1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name AddressPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init BitTransfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsTransmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WSPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name AddressScale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Uart Data Register 0xC0E4 R/W Transmit Full BitPin Diagram Pin DescriptionsPin Descriptions Name Type A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics Reset Timing AC Timing CharacteristicsClock Timing I2C Eeprom TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Document History Issue Orig. Description of Change Date
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