Cypress CY7C67200 I2C Eeprom Interface Pins Pin Name Pin Number, Serial Peripheral Interface

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CY7C67200

UART Features

•Supports baud rates of 900 to 115.2K

•8-N-1

UART Pins

Table 5. UART Interface Pins

Pin Name

Pin Number

TX

B5

 

 

RX

B4

 

 

I2C EEPROM Interface

EZ-OTG provides a master-only I2C interface for external se- rial EEPROMs. The serial EEPROM can be used to store ap- plication-specific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM interface is a BIOS imple- mentation and is exposed through GPIO pins. Refer to the BIOS documentation for additional details on this interface.

I2C EEPROM Features

•Supports EEPROMs up to 64 KB (512K bit)

•Auto-detection of EEPROM size

I2C EEPROM Pins

Table 6. I2C EEPROM Interface Pins

Pin Name

 

Pin Number

 

SMALL

EEPROM

 

 

 

SCK

 

H3

 

 

 

SDA

 

F3

 

 

 

 

LARGE

EEPROM

 

 

 

SCK

 

F3

 

 

 

SDA

 

H3

 

 

 

Serial Peripheral Interface

EZ-OTG provides an SPI interface for added connectivity. EZ-OTG may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Memory port.

SPI Features

•Master or slave mode operation

•DMA block transfer and PIO byte transfer modes

•Full duplex or half duplex data communication

•8-byte receive FIFO and 8-byte transmit FIFO

•Selectable master SPI clock rates from 250 kHz to 12 MHz

•Selectable master SPI clock phase and polarity

•Slave SPI signaling synchronization and filtering

•Slave SPI clock rates up to 2 MHz

•Maskable interrupts for block and byte transfer modes

•Individual bit transfer for non-byte aligned serial communi- cation in PIO mode

•Programmable delay timing for the active/inactive master SPI clock

•Auto or manual control for master mode slave select signal

•Complete access to internal memory

SPI Pins

The SPI port has a few different pin location options as shown in Table 7. The pin location is selectable via the GPIO Control register [0xC006].

Table 7. SPI Interface Pins

Pin Name

Pin Number

nSSI

F6 or C6

 

 

SCK

D5

 

 

MOSI

D4

 

 

MISO

C5

 

 

High-Speed Serial Interface

EZ-OTG provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to 2M baud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking. Complete control of EZ-OTG can be accom- plished through this interface via an extensible API and com- munication protocol. The HSS interface can be exposed through GPIO pins or the External Memory port.

HSS Features

•8-bit, no parity code

•Programmable baud rate from 9600 baud to 2M baud

•Selectable 1- or 2-stop bit on transmit

•Programmable intercharacter gap timing for Block Transmit

•8-byte receive FIFO

•Glitch filter on receive

•Block mode transfer directly to/from EZ-OTG internal memory (DMA transfer)

•Selectable CTS/RTS hardware signal handshake protocol

•Selectable XON/XOFF software handshake protocol

•Programmable Receive interrupt, Block Transfer Done interrupts

•Complete access to internal memory

HSS Pins

Table 8. HSS Interface Pins

Pin Name

Pin Number

CTS

F6

 

 

RTS

E4

 

 

RX

E5

 

 

TX

E6

 

 

Document #: 38-08014 Rev. *G

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Contents EZ-OTG Features Typical ApplicationsCY7C67200 CY16Processor Core Functional Overview IntroductionInterface Descriptions USB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceI2C Eeprom Interface Pins Pin Name Pin Number SPI Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Interface Pins 1 Pin Name Pin Number Host Port Interface HPIHPI Addressing HPI A10 Charge Pump InterfaceBooster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Crystal Pins Pin Name Pin Number Boot Configuration InterfaceBoot Mode PinPower Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Bank Register 0xC002 R/W Bank Register Example Hex Value Binary ValueReserved Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedHost/Device 2 Wake Enable Bit Host/Device 1 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitHalt Enable Bit OTG Interrupt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitUart Interrupt Enable Bit Gpio Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 2A Diagnostic Enable Bit Port 1A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitTimeout Flag Bit Lock Enable BitWDT Enable Bit Reset Strobe BitTimer n Register R/W General USB RegistersUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAMode Select Bit Port a Resistors Enable BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnablePreamble Enable Bit Sync Enable BitISO Enable Bit Arm Enable BitHost n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Error Flag Bit Underflow Flag BitStall Flag Bit NAK Flag BitACK Flag Bit Host n PID Register WPID Select Definition PID SelectHost n Count Result Register R Host n Device Address Register WVbus Interrupt Enable Bit ID Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitVbus Interrupt Flag Bit ID Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitCount Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R Host n Frame Register R USB Device Only Registers ReservedUSB Device Only Registers Register Name Address Device 1/DeviceIN/OUT Ignore Enable Bit Stall Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitSetup Flag Bit Timeout occurred Timeout condition did not occurError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register R/W SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable BitEP5 Interrupt Enable Bit EP2 Interrupt Enable Bit EP4 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WReset Interrupt Flag Bit EP7 Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Flag Bit SOF/EOP Timeout Interrupt Counter BitsDevice n Frame Number Register R Device n SOF/EOP Count Register WVbus Pull-up Enable Bit Receive Disable BitCharge Pump Enable Bit Vbus Discharge Enable BitWrite Protect Enable Bit SAS Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitHSS Enable Bit SPI Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address Xoff Enable Bit CTS Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitPacket Mode Select Bit Transmit Ready BitReceive Overflow Flag Bit Receive Packet Ready Flag BitTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WHPI Registers HPI Registers Register Name AddressVbus to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIEXmsg Register W SIE1msg Register SIE2msg RegisterData Bits HPI Mailbox Register 0xC0C6 R/WReset2 Flag Bit Vbus Flag BitID Flag Bit SOF/EOP2 Flag BitSPI Registers Reset1 Flag Bit Done1 Flag BitMailbox Out Flag Bit SPI Registers Register Name Address3Wire Enable Bit Phase Select BitMaster Active Enable Bit Master Enable BitByte Mode Bit Read Enable BitSCK Strobe Bit Fifo Init BitTransmit Interrupt Enable Bit Transfer Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsCRC Mode Definition CRCMode CRC Polynomial Transmit Interrupt Flag BitTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Enable Bit CRC Clear BitReceive CRC Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WSPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WUart Registers Uart Registers Register Name AddressUart Enable Bit Scale Select BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Descriptions Pin DiagramPin Descriptions Name Type GPIO20 General Purpose IO A1 HPI A1GPIO19 General Purpose IO A0 HPI A0Booster Power Input 2.7V to Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingI2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Data Access Time, from HPInRD falling HPI Host Port Interface Read Cycle TimingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Package Diagram Ordering InformationOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History
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