Cypress CY7C67200 manual HSS Byte Mode Transmit, HSS Block Mode Transmit

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CY7C67200

HSS BYTE Mode Transmit

qt_clk

CPU_A[2:0]

CPUHSS_cs

CPU_wr

TxRdy flag

HSS_TxD

Byte transmit triggered by a CPU write to the HSS_TxData register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU may start another BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

transmit right after TxRdy

 

 

 

 

 

 

 

 

 

 

 

 

 

 

goes high

 

BT

 

BT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

 

bit 7

stop bit start bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

start bit

bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TxRdy low to start bit delay:

 

 

 

 

start of last data bit to TxRdy high:

 

programmable

 

 

 

 

0 min, 4 T max.

 

 

 

 

 

 

0 min, BT max when starting from IDEL.

 

 

 

 

 

 

 

 

1 or 2 stop bits.

 

 

(T is qt_clk period)

 

 

 

 

 

 

For back to back transmit, new START Bit

 

 

 

 

 

 

 

 

1 stop bit shown.

 

 

 

 

 

 

 

 

 

 

begins immediately following previous STOP bit.

 

 

 

 

 

 

 

 

 

 

(BT = bit period)

qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera- tions and HSS port operations.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate.

HSS Block Mode Transmit

BT

HSS_TxD

t GAP

BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.

The BLOCK mode STOP bit time, tGAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS Transmit Gap register 90xC074].

The default tGAP is 2 BT. BT = bit time = 1/baud rate.

HSS BYTE and BLOCK Mode Receive

HSS_RxD

BT +/- 5%

 

 

 

 

 

 

received byte added to

 

 

 

 

 

 

 

 

 

 

 

 

BT +/- 5%

 

 

 

 

 

receive FIFO during the final data bit time

start bit

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit

start bit

 

 

 

 

10 BT +/- 5%

 

 

 

 

 

Receive data arrives asynchronously relative to the internal clock.

Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or higher).

BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag. BLOCK mode received bytes are written directly to the memory system.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate.

Document #: 38-08014 Rev. *G

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Contents CY16 EZ-OTG FeaturesTypical Applications CY7C67200Interface Descriptions IntroductionProcessor Core Functional Overview OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number USB InterfaceSerial Peripheral Interface I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number HSS Interface Pins Pin Name Pin NumberCharge Pump Interface HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI HPI Addressing HPI A10Crystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Pin Crystal Pins Pin Name Pin NumberBoot Configuration Interface Boot ModeSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHSS Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit OTG Wake Enable BitHost/Device 2 Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitTimer 0 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 1 Interrupt Enable BitLS Pull-up Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit Pull-down Enable BitReset Strobe Bit Timeout Flag BitLock Enable Bit WDT Enable Bit0xC08A/0xC0AA Timer n Register R/WGeneral USB Registers USB Registers Register Name Address SIE1/SIE2Resistors Function Select Enable Mode Select BitPort a Resistors Enable Bit USB Data Line Pull-up and Pull-down Resistors Mode Port nArm Enable Bit Preamble Enable BitSync Enable Bit ISO Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W NAK Flag Bit Error Flag BitUnderflow Flag Bit Stall Flag BitPID Select ACK Flag BitHost n PID Register W PID Select DefinitionHost n Device Address Register W Host n Count Result Register RPort a Wake Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit SOF/EOP Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration Register Name Address Device 1/Device Host n Frame Register RUSB Device Only Registers Reserved USB Device Only RegistersEnable Bit IN/OUT Ignore Enable BitStall Enable Bit NAK Interrupt Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WException Flag Bit Setup Flag BitTimeout occurred Timeout condition did not occur Error occurred Error did not occurDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WEP7 Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP1 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP3 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitDevice n SOF/EOP Count Register W SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n Frame Number Register RVbus Discharge Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Charge Pump Enable BitVbus Valid Flag Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 111 ReservedInterrupt 0 Polarity Select Bit HSS Enable BitSPI Enable Bit Interrupt 0 Enable BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers RTS Polarity Select Bit Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitReceive Packet Ready Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHPI Registers Register Name Address HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI RegistersHPI Breakpoint Register 0x0140 R Vbus to HPI Enable BitID to HPI Enable Bit SOF/EOP2 to HPI Enable BitReset2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit SOF/EOP1 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register Data BitsSOF/EOP2 Flag Bit Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Register Name Address SPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitFifo Init Bit Byte Mode BitRead Enable Bit SCK Strobe BitReceive Bit Length Bits Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Clear Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transfer Interrupt Flag BitOne in CRC Bit CRC Enable BitCRC Clear Bit Receive CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WUart Registers Register Name Address SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart RegistersUart Baud Select Definition Baud Rate DIV8 = Uart Enable BitScale Select Bit Baud Select BitsUart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Name Type Pin DiagramPin Descriptions A0 HPI A0 GPIO20 General Purpose IOA1 HPI A1 GPIO19 General Purpose IOCrystal Requirements XTALIN, Xtalout Booster Power Input 2.7V toAbsolute Maximum Ratings Operating ConditionsDC Characteristics Reset Timing AC Timing CharacteristicsParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Package DiagramOrdering Information Ordering Information Ordering Code Package Type PB-FreeDocument History Issue Orig. Description of Change Date
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