Cypress CY7C67200 manual Document History, Issue Orig. Description of Change Date

Page 78

CY7C67200

Document History Page

Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller

Document Number: 38-08014

	REV.	ECN NO.	Issue	Orig. of	Description of Change
	REV.	ECN NO.	Date	Change	Description of Change
			Date	Change

	**	111872	03/22/02	MUL	New Data Sheet

	*A	116988	08/23/02	MUL	Preliminary Data Sheet

	*B	124954	04/10/03	MUL	Added Memory Map Section and Ordering Information Section
					Moved Functional Register Map Tables into Register section
					General Clean-up
					Changed from “Preliminary“ to “Preliminary Confidential“
	*C	126211	05/23/03	MUL	Added Interface Description Section and Power Savings and Reset Section
					Added Char Data
					General Clean-up
					Removed DRAM, MDMA, and EPP
					Added “Programmable” to the title page
	*D	127334	05/29/03	KKV	Corrected font to enable correct symbol display

	*E	129394	10/07/03	MUL	Final Data Sheet
					Changed Memory Map Section
					Added USB OTG Logo
					General Clean-up
	*F	472875	See ECN	ARI	Removed “power consumption” bullet from the Features bullet list.
					Corrected number GPIO[31:20] to read GPIO[31:30] in Section “Standalone
					Mode”.
					Made sentence into a Note in Section “Reset Pin” and repeated the note in
					Section “Host Port Interface (HPI)”.
					Corrected the Host/Device 1 Interrupt Enable (Bit 8) Information in Section
					“Interrupt Enable Register [0xC00E] [R/W]”.
					Corrected data on Write Protect Enable (Bit 15) Section “GPIO Control
					Register [0xC006] [R/W]” to read “the GPIO Mode Select [15:8] bits are read
					only until a chip reset“.
					Re-wrote the Register Description in Section “SIEXmsg Register [W]”.
					Put document on 2-column template and corrected grammar. Put the figure
					captions at the top of the figures per new template specifications.
					Added Static Discharge Voltage information in Section “Absolute Maximum
					Ratings”
					Added compliance statement and TID in Section “USB Transceiver”.
	*G	567317	See ECN	KKVTMP	Added the lead free information on the Ordering Information Section. Imple-
					mented the new template with no numbers on the headings.

Document #: 38-08014 Rev. *G

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Contents CY7C67200 EZ-OTG FeaturesTypical Applications CY16Introduction Processor Core Functional OverviewInterface Descriptions USB Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number OTG InterfaceHSS Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Addressing HPI A10 HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI Charge Pump InterfaceCharge Pump Interface Pins Pin Name Pin Number Booster InterfaceCrystal Interface Boot Mode Crystal Pins Pin Name Pin NumberBoot Configuration Interface PinPower Savings and Reset Description Power Savings Mode DescriptionSleep Memory Map Registers Reserved Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedOTG Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit HSS Wake Enable BitSPI Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit Host/Device 2 Interrupt Enable BitTimer 1 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 0 Interrupt Enable BitPull-down Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit LS Pull-up Enable BitWDT Enable Bit Timeout Flag BitLock Enable Bit Reset Strobe BitUSB Registers Register Name Address SIE1/SIE2 Timer n Register R/WGeneral USB Registers 0xC08A/0xC0AAUSB Data Line Pull-up and Pull-down Resistors Mode Port n Mode Select BitPort a Resistors Enable Bit Resistors Function Select EnableISO Enable Bit Preamble Enable BitSync Enable Bit Arm Enable BitHost n Address Register R/W Host n Count Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Stall Flag Bit Error Flag BitUnderflow Flag Bit NAK Flag BitPID Select Definition ACK Flag BitHost n PID Register W PID SelectHost n Count Result Register R Host n Device Address Register WSOF/EOP Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit Port a Wake Interrupt Enable BitSOF/EOP Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Count Register R/W Count Bits Count field sets the SOF/EOP counter durationHost n SOF/EOP Counter Register R USB Device Only Registers Host n Frame Register RUSB Device Only Registers Reserved Register Name Address Device 1/DeviceNAK Interrupt Enable Bit IN/OUT Ignore Enable BitStall Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitError occurred Error did not occur Setup Flag BitTimeout occurred Timeout condition did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterReset Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit EP7 Interrupt Enable BitEP3 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitDevice n Frame Number Register R SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n SOF/EOP Count Register WCharge Pump Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Vbus Discharge Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Write Protect Enable BitSAS Enable Bit Vbus Valid Flag BitInterrupt 0 Enable Bit HSS Enable BitSPI Enable Bit Interrupt 0 Polarity Select BitGpio 0 Input Data Register 0xC020 R Gpio 1 Input Data Register 0xC026 RGpio 0 Direction Register 0xC022 R/W Gpio 1 Direction Register 0xC028 R/W HSS RegistersHSS Registers Register Name Address Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit RTS Polarity Select BitReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Packet Ready Flag BitHSS Transmit Gap Register 0xC074 R/W Transmit Gap Select BitsHSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHPI Registers HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers Register Name AddressSOF/EOP2 to HPI Enable Bit Vbus to HPI Enable BitID to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to CPU Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit Reset2 to HPI Enable BitData Bits SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WID Flag Bit Reset2 Flag BitVbus Flag Bit SOF/EOP2 Flag BitMailbox Out Flag Bit SPI Registers Reset1 Flag BitDone1 Flag Bit SPI Registers Register Name AddressMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit Fifo Init BitFifo Error Flag Bit Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Receive Bit Length BitsTransfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transmit Interrupt Clear BitReceive CRC Bit CRC Enable BitCRC Clear Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WUart Registers SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Register Name AddressBaud Select Bits Uart Enable BitScale Select Bit Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Diagram Pin DescriptionsPin Descriptions Name Type GPIO19 General Purpose IO GPIO20 General Purpose IOA1 HPI A1 A0 HPI A0Operating Conditions Booster Power Input 2.7V toAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingClock Timing I2C Eeprom TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Pulse Width Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time Document # 38-08014 Rev. *GHSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Ordering Code Package Type PB-Free Package DiagramOrdering Information Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History