Cypress CY7C67200 manual Device n Frame Number Register R, SOF/EOP Timeout Flag Bit

Page 38

CY7C67200

Device n Frame Number Register [R]

•Device 1 Frame Number Register 0xC092

•Device 2 Frame Number Register 0xC0B2

Figure 38. Device n Frame Number Register

Bit #

15

14

 

13

 

12

11

10

9

8

Field

SOF/EOP

 

 

SOF/EOP

 

Reserved

 

Frame...

 

Timeout Flag

 

Timeout Interrupt Counter

 

 

 

 

 

Read/Write

R

R

 

R

 

R

-

R

R

R

Default

0

0

 

0

 

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

 

3

2

1

0

Field

 

 

 

 

...Frame

 

 

 

Read/Write

R

R

R

R

 

R

R

R

R

Default

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

Register Description

The Device n Frame Number register is a read only register that contains the Frame number of the last SOF packet received. This register also contains a count of SOF/EOP Timeout occurrences.

SOF/EOP Timeout Flag (Bit 15)

The SOF/EOP Timeout Flag bit indicates when an SOF/EOP Timeout Interrupt occurs.

1:An SOF/EOP Timeout interrupt occurred

0:An SOF/EOP Timeout interrupt did not occur

SOF/EOP Timeout Interrupt Counter (Bits [14:12])

The SOF/EOP Timeout Interrupt Counter field increments by 1 from 0 to 7 for each SOF/EOP Timeout Interrupt. This field resets to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Timeout Interrupt Enable bit in the Device n Interrupt Enable register is set.

Frame (Bits [10:0])

The Frame field contains the frame number from the last received SOF packet in full speed mode. This field has no function for low-speed mode. If a SOF Timeout occurs, this field contains the last received Frame number.

Device n SOF/EOP Count Register [W]

•Device 1 SOF/EOP Count Register 0xC094

•Device 2 SOF/EOP Count Register 0xC0B4

Figure 39. Device n SOF/EOP Count Register

Bit #

15

 

14

13

12

11

 

10

9

8

Field

Reserved

 

 

 

 

Count...

 

 

Read/Write

-

 

-

R

R

R

 

R

R

R

Default

0

 

0

1

0

1

 

1

1

0

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

 

3

2

1

0

Field

 

 

 

 

...Count

 

 

 

Read/Write

R

R

R

R

 

R

R

R

R

Default

1

1

1

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

Register Description

The Device n SOF/EOP Count register must be written with the time expected between receiving a SOF/EOPs. If the SOF/EOP counter expires before an SOF/EOP is received, an SOF/EOP Timeout Interrupt can be generated. The SOF/EOP Timeout Interrupt Enable and SOF/EOP Timeout Interrupt Flag are located in the Device n Interrupt Enable and Status registers, respectively.

The SOF/EOP count must be set slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decre- ments at a 12-MHz rate. Therefore in the case of an expected

1-ms SOF/EOP interval, the SOF/EOP count must be set slightly greater then 0x2EE0.

Count (Bits [13:0])

The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Contents CY7C67200 EZ-OTG FeaturesTypical Applications CY16Interface Descriptions IntroductionProcessor Core Functional Overview USB Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number OTG InterfaceHSS Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Addressing HPI A10 HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI Charge Pump InterfaceCrystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Boot Mode Crystal Pins Pin Name Pin NumberBoot Configuration Interface PinSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Reserved Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedOTG Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit HSS Wake Enable BitSPI Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit Host/Device 2 Interrupt Enable BitTimer 1 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 0 Interrupt Enable BitPull-down Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit LS Pull-up Enable BitWDT Enable Bit Timeout Flag BitLock Enable Bit Reset Strobe BitUSB Registers Register Name Address SIE1/SIE2 Timer n Register R/WGeneral USB Registers 0xC08A/0xC0AAUSB Data Line Pull-up and Pull-down Resistors Mode Port n Mode Select BitPort a Resistors Enable Bit Resistors Function Select EnableISO Enable Bit Preamble Enable BitSync Enable Bit Arm Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Stall Flag Bit Error Flag BitUnderflow Flag Bit NAK Flag BitPID Select Definition ACK Flag BitHost n PID Register W PID SelectHost n Count Result Register R Host n Device Address Register WSOF/EOP Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit Port a Wake Interrupt Enable BitSOF/EOP Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration USB Device Only Registers Host n Frame Register RUSB Device Only Registers Reserved Register Name Address Device 1/DeviceNAK Interrupt Enable Bit IN/OUT Ignore Enable BitStall Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitError occurred Error did not occur Setup Flag BitTimeout occurred Timeout condition did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterReset Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit EP7 Interrupt Enable BitEP3 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitDevice n Frame Number Register R SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n SOF/EOP Count Register WCharge Pump Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Vbus Discharge Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Write Protect Enable BitSAS Enable Bit Vbus Valid Flag BitInterrupt 0 Enable Bit HSS Enable BitSPI Enable Bit Interrupt 0 Polarity Select BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit RTS Polarity Select BitReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Packet Ready Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHPI Registers HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers Register Name AddressSOF/EOP2 to HPI Enable Bit Vbus to HPI Enable BitID to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to CPU Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit Reset2 to HPI Enable BitData Bits SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WID Flag Bit Reset2 Flag BitVbus Flag Bit SOF/EOP2 Flag BitMailbox Out Flag Bit SPI Registers Reset1 Flag BitDone1 Flag Bit SPI Registers Register Name AddressMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit Fifo Init BitFifo Error Flag Bit Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Receive Bit Length BitsTransfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transmit Interrupt Clear BitReceive CRC Bit CRC Enable BitCRC Clear Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WUart Registers SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Register Name AddressBaud Select Bits Uart Enable BitScale Select Bit Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Descriptions Name Type Pin DiagramPin Descriptions GPIO19 General Purpose IO GPIO20 General Purpose IOA1 HPI A1 A0 HPI A0Operating Conditions Booster Power Input 2.7V toAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing Read Pulse Width Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time Document # 38-08014 Rev. *GHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Ordering Code Package Type PB-Free Package DiagramOrdering Information Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History
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