Cypress CY7C67200 SCK Strobe Bit, Fifo Init Bit, Byte Mode Bit, Full Duplex Bit, Read Enable Bit

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CY7C67200

SPI Control Register [0xC0CA] [R/W]

Figure 62. SPI Control Register

Bit #

15

14

13

12

11

10

9

8

Field

SCK

FIFO

Byte

Full Duplex

SS

Read

Transmit

Receive

Strobe

Init

Mode

 

Manual

Enable

Ready

Data Ready

Read/Write

W

W

R/W

R/W

R/w

R/W

R

R

Default

0

0

0

0

0

0

0

1

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

 

4

 

3

2

 

1

 

0

Field

Transmit

Receive

 

Transmit Bit Length

 

 

Receive Bit Length

 

Empty

Full

 

 

 

 

 

 

 

 

 

 

Read/Write

R

R

R/W

 

R/W

 

R/W

R/W

 

R/w

 

R/W

Default

1

0

0

 

0

 

0

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Description

The SPI Control register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.

SCK Strobe (Bit 15)

The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration register), but not phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self-clearing.

1:SCK Strobe Enable

0:No Function

FIFO Init (Bit 14)

The FIFO Init bit initializes the FIFO and clear the FIFO Error Status bit. This bit is self-clearing.

1:FIFO Init Enable

0:No Function

Byte Mode (Bit 13)

The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation.

1:Set PIO (byte mode) operation

0:Set DMA (block mode) operation

Full Duplex (Bit 12)

The Full Duplex bit selects between full-duplex and half-duplex operation.

1:Enable full duplex. Full duplex is not allowed and will not set if the 3Wire Enable bit of the SPI Configuration register is set to ‘1’

0:Enable half-duplex operation

SSManual (Bit 11)

The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control register is all zeros and is configured as master interface. This field only applies to master mode.

1:Activate SS, master drives SS line asserted LOW

0:Deactivate SS, master drives SS line deasserted HIGH

Read Enable (Bit 10)

The Read Enable bit initiates a read phase for a master mode transfer or set the slave to receive (in slave mode).

1:Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set until the read transfer begins.

0:Initiates the write phase for slave operation

Transmit Ready (Bit 9)

The Transmit Ready bit is a read-only bit that indicates if the transmit port is ready to empty and ready to be written.

1:Ready for data to be written to the port. The transmit FIFO is not full.

0:Not ready for data to be written to the port

Receive Data Ready (Bit 8)

The Receive Data Ready bit is a read-only bit that indicates if the receive port has data ready.

1:Receive port has data ready to read

0:Receive port does not have data ready

Transmit Empty (Bit 7)

The Transmit Empty bit is a read-only bit that indicates if the transmit FIFO is empty.

1:Transmit FIFO is empty

0:Transmit FIFO is not empty

Receive Full (Bit 6)

The Receive Full bit is a read-only bit that indicates if the receive FIFO is full.

1:Receive FIFO is full

0:Receive FIFO is not full

Transmit Bit Length (Bits [5:3])

The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted. If Transmit Bit Length is ‘000’, a full byte is transmitted. If Transmit Bit Length is ‘001’ to ‘111’, the value indicates the number of bits that will be transmitted.

Document #: 38-08014 Rev. *G

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Contents CY16 EZ-OTG FeaturesTypical Applications CY7C67200Processor Core Functional Overview IntroductionInterface Descriptions OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number USB InterfaceSerial Peripheral Interface I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number HSS Interface Pins Pin Name Pin NumberCharge Pump Interface HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI HPI Addressing HPI A10Booster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Pin Crystal Pins Pin Name Pin NumberBoot Configuration Interface Boot ModePower Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHSS Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit OTG Wake Enable BitHost/Device 2 Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitTimer 0 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 1 Interrupt Enable BitLS Pull-up Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit Pull-down Enable BitReset Strobe Bit Timeout Flag BitLock Enable Bit WDT Enable Bit0xC08A/0xC0AA Timer n Register R/WGeneral USB Registers USB Registers Register Name Address SIE1/SIE2Resistors Function Select Enable Mode Select BitPort a Resistors Enable Bit USB Data Line Pull-up and Pull-down Resistors Mode Port nArm Enable Bit Preamble Enable BitSync Enable Bit ISO Enable BitHost n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 NAK Flag Bit Error Flag BitUnderflow Flag Bit Stall Flag BitPID Select ACK Flag BitHost n PID Register W PID Select DefinitionHost n Device Address Register W Host n Count Result Register RPort a Wake Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit SOF/EOP Interrupt Flag BitCount Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R Register Name Address Device 1/Device Host n Frame Register RUSB Device Only Registers Reserved USB Device Only RegistersEnable Bit IN/OUT Ignore Enable BitStall Enable Bit NAK Interrupt Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WException Flag Bit Setup Flag BitTimeout occurred Timeout condition did not occur Error occurred Error did not occurDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WEP7 Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP1 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP3 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitDevice n SOF/EOP Count Register W SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n Frame Number Register RVbus Discharge Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Charge Pump Enable BitVbus Valid Flag Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 111 ReservedInterrupt 0 Polarity Select Bit HSS Enable BitSPI Enable Bit Interrupt 0 Enable BitGpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address RTS Polarity Select Bit Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitReceive Packet Ready Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHPI Registers Register Name Address HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI RegistersHPI Breakpoint Register 0x0140 R Vbus to HPI Enable BitID to HPI Enable Bit SOF/EOP2 to HPI Enable BitReset2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit SOF/EOP1 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register Data BitsSOF/EOP2 Flag Bit Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Register Name Address SPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitFifo Init Bit Byte Mode BitRead Enable Bit SCK Strobe BitReceive Bit Length Bits Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Clear Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transfer Interrupt Flag BitOne in CRC Bit CRC Enable BitCRC Clear Bit Receive CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WUart Registers Register Name Address SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart RegistersUart Baud Select Definition Baud Rate DIV8 = Uart Enable BitScale Select Bit Baud Select BitsUart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Pin DiagramPin Descriptions Name Type A0 HPI A0 GPIO20 General Purpose IOA1 HPI A1 GPIO19 General Purpose IOCrystal Requirements XTALIN, Xtalout Booster Power Input 2.7V toAbsolute Maximum Ratings Operating ConditionsDC Characteristics Reset Timing AC Timing CharacteristicsI2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Package DiagramOrdering Information Ordering Information Ordering Code Package Type PB-FreeDocument History Issue Orig. Description of Change Date
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