Cypress CY7C67200 manual USB Interface Pins Pin Name Pin Number, OTG Interface, Uart Interface

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CY7C67200

USB Interface

EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specification requirements for full and low speed (high speed is not support- ed). In Host mode, EZ-OTG supports two downstream ports; each supports control, interrupt, bulk, and isochronous trans- fers. In Peripheral mode, EZ-OTG supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support Interrupt, bulk (up to 64 bytes per packet), or isochronous transfers (up to 1023 bytes per packet size). EZ-OTG also supports a combination of Host and Peripheral ports simultaneously, as shown in Table 2.

Table 2. USB Port Configuration Options

 

Port Configurations

Port 1A

Port 2A

OTG

OTG

–

 

 

 

OTG + 1 Host

OTG

Host

 

 

 

OTG + 1 Peripheral

OTG

Peripheral

 

 

 

 

1

Host + 1 Peripheral

Host

Peripheral

 

 

 

 

1

Host + 1 Peripheral

Peripheral

Host

 

 

 

 

2

Hosts

Host

Host

 

 

 

 

1

Host

Host

–

 

 

 

 

1

Host

–

Host

 

 

 

 

2

Peripherals

Peripheral

Peripheral

 

 

 

 

1

Peripheral

Peripheral

–

 

 

 

 

1

Peripheral

–

Peripheral

 

 

 

 

USB Features

•USB 2.0 compatible for full and low speed

•Up to two downstream USB host ports

•Up to two upstream USB peripheral ports

•Configurable endpoint buffers (pointer and length), must reside in internal RAM

•Up to eight available peripheral endpoints (1 control endpoint)

•Supports Control, Interrupt, Bulk, and Isochronous transfers

•Internal DMA channels for each endpoint

•Internal pull up and pull down resistors

•Internal Series termination resistors on USB data lines

USB Pins

Table 3. USB Interface Pins

Pin Name

Pin Number

DM1A

F2

 

 

DP1A

E3

 

 

DM2A

C2

 

 

DP2A

D3

 

 

OTG Interface

EZ-OTG has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG port has various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is only supported on USB PORT 1A.

OTG Features

•Internal Charge Pump to supply and control VBUS

•VBUS Valid Status (above 4.4V)

•VBUS Status for 2.4V < VBUS < 0.8V

•ID Pin Status

•Switchable 2-Kohm internal discharge resistor on VBUS

•Switchable 500-ohm internal pull-up resistor on VBUS

•Individually switchable internal pull-up and pull-down resistors on the USB data lines

OTG Pins

Table 4. OTG Interface Pins

Pin Name

Pin Number

DM1A

F2

 

 

DP1A

E3

 

 

OTGVBUS

C1

 

 

OTGID

F4

 

 

CSwitchA

D1

 

 

CSwitchB

D2

 

 

General Purpose IO Interface

EZ-OTG has up to 25 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs.

GPIO Description

All Inputs are sampled asynchronously with state changes oc- curring at a rate of up to two 48 MHz clock cycles. GPIO pins are latched directly into registers, a single flip-flop.

Unused Pin Descriptions

Unused USB pins must be tri-stated with the D+ line pulled high through the internal pull-up resistor and the D– line pulled low through the internal pull-down resistor.

Unused GPIO pins must be configured as outputs and driven low.

UART Interface

EZ-OTG has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The UART interface is exposed through GPIO pins.

Document #: 38-08014 Rev. *G

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Contents CY16 EZ-OTG FeaturesTypical Applications CY7C67200Introduction Processor Core Functional OverviewInterface Descriptions OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number USB InterfaceSerial Peripheral Interface I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number HSS Interface Pins Pin Name Pin NumberCharge Pump Interface HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI HPI Addressing HPI A10Charge Pump Interface Pins Pin Name Pin Number Booster InterfaceCrystal Interface Pin Crystal Pins Pin Name Pin NumberBoot Configuration Interface Boot ModePower Savings and Reset Description Power Savings Mode DescriptionSleep Memory Map Registers Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value ReservedCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHSS Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit OTG Wake Enable BitHost/Device 2 Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable BitTimer 0 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 1 Interrupt Enable BitLS Pull-up Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit Pull-down Enable BitReset Strobe Bit Timeout Flag BitLock Enable Bit WDT Enable Bit0xC08A/0xC0AA Timer n Register R/WGeneral USB Registers USB Registers Register Name Address SIE1/SIE2Resistors Function Select Enable Mode Select BitPort a Resistors Enable Bit USB Data Line Pull-up and Pull-down Resistors Mode Port nArm Enable Bit Preamble Enable BitSync Enable Bit ISO Enable BitHost n Address Register R/W Host n Count Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 NAK Flag Bit Error Flag BitUnderflow Flag Bit Stall Flag BitPID Select ACK Flag BitHost n PID Register W PID Select DefinitionHost n Device Address Register W Host n Count Result Register RPort a Wake Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort a Wake Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit SOF/EOP Interrupt Flag BitHost n SOF/EOP Count Register R/W Count Bits Count field sets the SOF/EOP counter durationHost n SOF/EOP Counter Register R Register Name Address Device 1/Device Host n Frame Register RUSB Device Only Registers Reserved USB Device Only RegistersEnable Bit IN/OUT Ignore Enable BitStall Enable Bit NAK Interrupt Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WException Flag Bit Setup Flag BitTimeout occurred Timeout condition did not occur Error occurred Error did not occurDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WEP7 Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP1 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP3 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag BitDevice n SOF/EOP Count Register W SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n Frame Number Register RVbus Discharge Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Charge Pump Enable BitVbus Valid Flag Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 111 ReservedInterrupt 0 Polarity Select Bit HSS Enable BitSPI Enable Bit Interrupt 0 Enable BitGpio 0 Input Data Register 0xC020 R Gpio 1 Input Data Register 0xC026 RGpio 0 Direction Register 0xC022 R/W Gpio 1 Direction Register 0xC028 R/W HSS RegistersHSS Registers Register Name Address RTS Polarity Select Bit Xoff Enable BitCTS Enable Bit Receive Interrupt Enable BitReceive Packet Ready Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag BitHSS Transmit Gap Register 0xC074 R/W Transmit Gap Select BitsHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHPI Registers Register Name Address HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI RegistersHPI Breakpoint Register 0x0140 R Vbus to HPI Enable BitID to HPI Enable Bit SOF/EOP2 to HPI Enable BitReset2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit SOF/EOP1 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register Data BitsSOF/EOP2 Flag Bit Reset2 Flag BitVbus Flag Bit ID Flag BitSPI Registers Register Name Address SPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag BitMaster Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable BitFifo Init Bit Byte Mode BitRead Enable Bit SCK Strobe BitReceive Bit Length Bits Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag BitTransmit Interrupt Clear Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transfer Interrupt Flag BitOne in CRC Bit CRC Enable BitCRC Clear Bit Receive CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WUart Registers Register Name Address SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart RegistersUart Baud Select Definition Baud Rate DIV8 = Uart Enable BitScale Select Bit Baud Select BitsUart Data Register 0xC0E4 R/W Transmit Full BitPin Diagram Pin DescriptionsPin Descriptions Name Type A0 HPI A0 GPIO20 General Purpose IOA1 HPI A1 GPIO19 General Purpose IOCrystal Requirements XTALIN, Xtalout Booster Power Input 2.7V toAbsolute Maximum Ratings Operating ConditionsDC Characteristics Reset Timing AC Timing CharacteristicsClock Timing I2C Eeprom TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse WidthHSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Package DiagramOrdering Information Ordering Information Ordering Code Package Type PB-FreeDocument History Issue Orig. Description of Change Date
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