Cypress CY7C67200 Vbus Valid Flag Bit, Gpio Registers Register Name Address, SAS Enable Bit

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CY7C67200

VBUS Valid Flag (Bit 0)

The VBUS Valid Flag bit indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware should wait at least 10 µs before this reading this bit.

GPIO Registers

1:OTG VBus is greater then 4.4V

0:OTG VBus is less then 4.4V

Reserved

All reserved bits must be written as ‘0’.

There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in Table 29.

Table 29.GPIO Registers

 

Register Name

 

 

 

 

Address

 

 

R/W

 

GPIO Control Register

 

 

 

 

 

0xC006

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO0 Output Data Register

 

 

 

 

 

0xC01E

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO0 Input Data Register

 

 

 

 

 

0xC020

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO0 Direction Register

 

 

 

 

 

0xC022

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO1 Output Data Register

 

 

 

 

 

0xC024

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO1 Input Data Register

 

 

 

 

 

0xC026

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO1 Direction Register

 

 

 

 

 

0xC028

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO Control Register [0xC006] [R/W]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 41. GPIO Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

15

 

14

13

 

12

 

11

 

10

9

8

 

Field

Write Protect

 

Reserved

Reserved

 

 

SAS

 

 

 

Mode

 

 

Enable

 

 

 

 

 

 

Enable

 

 

 

Select

 

 

Read/Write

R/W

 

-

R

 

-

 

R/W

 

R/W

 

R/W

R/W

 

Default

0

 

0

0

 

0

 

0

 

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

 

6

5

 

4

 

3

 

2

1

0

 

Field

HSS

 

Reserved

SPI

 

 

 

Reserved

 

 

Interrupt 0

Interrupt 0

 

Enable

 

 

Enable

 

 

 

 

 

 

Polarity Select

Enable

 

Read/Write

R/W

 

-

R/W

 

-

 

-

 

-

 

R/W

R/W

 

Default

0

 

0

0

 

0

 

0

 

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Description

The GPIO Control register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt on IRQ0 (GPIO24).

Write Protect Enable (Bit 15)

The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select [15:8] bits are read-only until a chip reset.

1:Enable Write Protect

0:Disable Write Protect

SAS Enable (Bit 11)

The SAS Enable bit, when in SPI mode, reroutes the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9].

1:Reroute SPI_nss to GPIO[15]

0:Leave SPI_nss on GPIO[9]

Mode Select (Bits [10:8])

The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table 30.

Table 30.Mode Select Definition

Mode Select

GPIO Configuration

[10:8]

 

111

Reserved

110SCAN – (HW) Scan diagnostic. For produc- tion test only. Not for normal operation

101HPI – Host Port Interface

100Reserved

011Reserved

010Reserved

001Reserved

000GPIO – General Purpose Input Output

Document #: 38-08014 Rev. *G

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Contents EZ-OTG Features Typical ApplicationsCY7C67200 CY16Processor Core Functional Overview IntroductionInterface Descriptions USB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceI2C Eeprom Interface Pins Pin Name Pin Number SPI Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Interface Pins 1 Pin Name Pin Number Host Port Interface HPIHPI Addressing HPI A10 Charge Pump InterfaceBooster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Crystal Pins Pin Name Pin Number Boot Configuration InterfaceBoot Mode PinPower Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Bank Register 0xC002 R/W Bank Register Example Hex Value Binary ValueReserved Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedHost/Device 2 Wake Enable Bit Host/Device 1 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitHalt Enable Bit OTG Interrupt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitUart Interrupt Enable Bit Gpio Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 2A Diagnostic Enable Bit Port 1A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitTimeout Flag Bit Lock Enable BitWDT Enable Bit Reset Strobe BitTimer n Register R/W General USB RegistersUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAMode Select Bit Port a Resistors Enable BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnablePreamble Enable Bit Sync Enable BitISO Enable Bit Arm Enable BitHost n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Error Flag Bit Underflow Flag BitStall Flag Bit NAK Flag BitACK Flag Bit Host n PID Register WPID Select Definition PID SelectHost n Count Result Register R Host n Device Address Register WVbus Interrupt Enable Bit ID Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitVbus Interrupt Flag Bit ID Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitCount Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R Host n Frame Register R USB Device Only Registers ReservedUSB Device Only Registers Register Name Address Device 1/DeviceIN/OUT Ignore Enable Bit Stall Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitSetup Flag Bit Timeout occurred Timeout condition did not occurError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register R/W SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable BitEP5 Interrupt Enable Bit EP2 Interrupt Enable Bit EP4 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WReset Interrupt Flag Bit EP7 Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Flag Bit SOF/EOP Timeout Interrupt Counter BitsDevice n Frame Number Register R Device n SOF/EOP Count Register WVbus Pull-up Enable Bit Receive Disable BitCharge Pump Enable Bit Vbus Discharge Enable BitWrite Protect Enable Bit SAS Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitHSS Enable Bit SPI Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address Xoff Enable Bit CTS Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitPacket Mode Select Bit Transmit Ready BitReceive Overflow Flag Bit Receive Packet Ready Flag BitTransmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WHPI Registers HPI Registers Register Name AddressVbus to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIEXmsg Register W SIE1msg Register SIE2msg RegisterData Bits HPI Mailbox Register 0xC0C6 R/WReset2 Flag Bit Vbus Flag BitID Flag Bit SOF/EOP2 Flag BitSPI Registers Reset1 Flag Bit Done1 Flag BitMailbox Out Flag Bit SPI Registers Register Name Address3Wire Enable Bit Phase Select BitMaster Active Enable Bit Master Enable BitByte Mode Bit Read Enable BitSCK Strobe Bit Fifo Init BitTransmit Interrupt Enable Bit Transfer Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsCRC Mode Definition CRCMode CRC Polynomial Transmit Interrupt Flag BitTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Enable Bit CRC Clear BitReceive CRC Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WSPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WUart Registers Uart Registers Register Name AddressUart Enable Bit Scale Select BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Descriptions Pin DiagramPin Descriptions Name Type GPIO20 General Purpose IO A1 HPI A1GPIO19 General Purpose IO A0 HPI A0Booster Power Input 2.7V to Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingI2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Data Access Time, from HPInRD falling HPI Host Port Interface Read Cycle TimingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Package Diagram Ordering InformationOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History
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