Cypress CY7C67200 manual HSS Enable Bit, SPI Enable Bit, Interrupt 0 Polarity Select Bit

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CY7C67200

HSS Enable (Bit 7)

The HSS Enable bit routes HSS to GPIO[15:12].

1:HSS is routed to GPIO

0:HSS is not routed to GPIOs. GPIO[15:12] are free for other purposes.

SPI Enable (Bit 5)

The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it overrides and routes the SPI_nSSI pin to GPIO15.

1:SPI is routed to GPIO[11:8]

0:SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes.

GPIO 0 Output Data Register [0xC01E] [R/W]

Interrupt 0 Polarity Select (Bit 1)

The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.

1:Sets IRQ0 to rising edge

0:Sets IRQ0 to falling edge

Interrupt 0 Enable (Bit 0)

The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled.

1:Enable IRQ0

0:Disable IRQ0

Reserved

All reserved bits must be written as ‘0’.

Figure 42. GPIO 0 Output Data Register

Bit #	15	14	13	12	11	10	9	8
Field	GPIO15	GPIO14	GPIO13	GPIO12	GPIO11	GPIO10	GPIO9	GPIO8
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	GPIO7	GPIO6	GPIO5	GPIO4	GPIO3	GPIO2	GPIO1	GPIO0
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Register Description

The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register).

Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.

Reserved

All reserved bits must be written as ‘0’.

GPIO 1 Output Data Register [0xC024] [R/W]

Figure 43. GPIO n Output Data Register

Bit #	15	14	13	12	11		10	9	8
Field	GPIO31	GPIO30	GPIO29			Reserved			GPIO24
Read/Write	R/W	R/W	R/W	-	-		-	-	R/W
Default	0	0	0	0	0		0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	GPIO23	GPIO22	GPIO21	GPIO20	GPIO19		Reserved
Read/Write	R/W	R/W	R/W	R/W	R/W	-	-	-
Default	0	0	0	0	0	0	0	0

Register Description

The GPIO 1 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register).

Document #: 38-08014 Rev. *G

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Contents Typical Applications EZ-OTG FeaturesCY7C67200 CY16Interface Descriptions IntroductionProcessor Core Functional Overview OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceSPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHost Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump InterfaceCrystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode PinSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 RCPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/WHost/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitOTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitGpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitLock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe BitGeneral USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAPort a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnableSync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag BitHost n PID Register W ACK Flag BitPID Select Definition PID SelectHost n Device Address Register W Host n Count Result Register RID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/DeviceStall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WOUT Exception Flag Bit Device n Endpoint n Status Register R/WTimeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/WSOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable BitEP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Status Register R/W Device n Address Register WEP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register WReceive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable BitSAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitSPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitTransmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WHSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name AddressID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/WVbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag BitDone1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name AddressPhase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable BitRead Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init BitTransfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsTransmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC BitSPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WSPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name AddressScale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Uart Data Register 0xC0E4 R/W Transmit Full BitPin Descriptions Name Type Pin DiagramPin Descriptions A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics Reset Timing AC Timing CharacteristicsParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hssrts Hsscts Hardware CTS/RTS HandshakeRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Document History Issue Orig. Description of Change Date