Cypress CY7C67200 manual Halt Enable Bit, OTG Interrupt Enable Bit, SPI Interrupt Enable Bit

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CY7C67200

Halt Enable (Bit 0)

Setting this bit to ‘1’ immediately initiates HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The power savings using HALT in most cases will be minimal, but in applications that are very CPU intensive the incremental savings may provide some benefit.

The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions

immediately following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow the HALT instruction with two NOPs).

1:Enable Halt Mode

0:No Function

Reserved

All reserved bits must be written as ‘0’.

Interrupt Enable Register [0xC00E] [R/W]

Figure 12. Interrupt Enable Register

Bit #

15

14

13

12

11

10

9

8

 

 

Reserved

 

OTG

SPI

Reserved

Host/Device 2

Host/Device 1

Field

 

 

 

Interrupt

Interrupt

 

Interrupt

Interrupt

 

 

 

Enable

Enable

 

Enable

Enable

Read/Write

-

-

-

R/W

R/W

-

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

 

HSS

In Mailbox

Out Mailbox

Reserved

UART

GPIO

Timer 1

Timer 0

Field

Interrupt

Interrupt

Interrupt

 

Interrupt

Interrupt

Interrupt

Interrupt

Enable

Enable

Enable

 

Enable

Enable

Enable

Enable

Read/Write

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

Default

0

0

0

1

0

0

0

0

 

 

 

 

 

 

 

 

 

Register Description

The Interrupt Enable Register allows control of the hardware interrupt vectors.

OTG Interrupt Enable (Bit 12)

The OTG Interrupt Enable bit enables or disables the OTG ID/OTG4.4V Valid hardware interrupt.

1:Enable OTG interrupt

0:Disable OTG interrupt

SPI Interrupt Enable (Bit 11)

The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block Done.

1:Enable SPI interrupt

0:Disable SPI interrupt

Host/Device 2 Interrupt Enable (Bit 9)

The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB Done, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device 2 Endpoint n.

1:Enable Host 2 and Device 2 interrupt

0:Disable Host 2 and Device 2 interrupt

Host/Device 1 Interrupt Enable (Bit 8)

The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB Done, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1 Endpoint n.

1:Enable Host 1 and Device 1 interrupt

0:Disable Host 1 and Device 1 interrupt

HSS Interrupt Enable (Bit 7)

The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done, and HSS RX Full.

1:Enable HSS interrupt

0:Disable HSS interrupt

In Mailbox Interrupt Enable (Bit 6)

The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.

1:Enable MBXI interrupt

0:Disable MBXI interrupt

Out Mailbox Interrupt Enable (Bit 5)

The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt.

1:Enable MBXO interrupt

0:Disable MBXO interrupt

Document #: 38-08014 Rev. *G

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Contents CY7C67200 EZ-OTG FeaturesTypical Applications CY16Interface Descriptions IntroductionProcessor Core Functional Overview USB Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number OTG InterfaceHSS Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Addressing HPI A10 HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI Charge Pump InterfaceCrystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Boot Mode Crystal Pins Pin Name Pin NumberBoot Configuration Interface PinSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Reserved Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedOTG Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit HSS Wake Enable BitSPI Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit Host/Device 2 Interrupt Enable BitTimer 1 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 0 Interrupt Enable BitPull-down Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit LS Pull-up Enable BitWDT Enable Bit Timeout Flag BitLock Enable Bit Reset Strobe BitUSB Registers Register Name Address SIE1/SIE2 Timer n Register R/WGeneral USB Registers 0xC08A/0xC0AAUSB Data Line Pull-up and Pull-down Resistors Mode Port n Mode Select BitPort a Resistors Enable Bit Resistors Function Select EnableISO Enable Bit Preamble Enable BitSync Enable Bit Arm Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Stall Flag Bit Error Flag BitUnderflow Flag Bit NAK Flag BitPID Select Definition ACK Flag BitHost n PID Register W PID SelectHost n Count Result Register R Host n Device Address Register WSOF/EOP Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit Port a Wake Interrupt Enable BitSOF/EOP Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration USB Device Only Registers Host n Frame Register RUSB Device Only Registers Reserved Register Name Address Device 1/DeviceNAK Interrupt Enable Bit IN/OUT Ignore Enable BitStall Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitError occurred Error did not occur Setup Flag BitTimeout occurred Timeout condition did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterReset Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit EP7 Interrupt Enable BitEP3 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WEP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag BitDevice n Frame Number Register R SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n SOF/EOP Count Register WCharge Pump Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Vbus Discharge Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Write Protect Enable BitSAS Enable Bit Vbus Valid Flag BitInterrupt 0 Enable Bit HSS Enable BitSPI Enable Bit Interrupt 0 Polarity Select BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit RTS Polarity Select BitReceive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Packet Ready Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHPI Registers HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers Register Name AddressSOF/EOP2 to HPI Enable Bit Vbus to HPI Enable BitID to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP1 to CPU Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit Reset2 to HPI Enable BitData Bits SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/WID Flag Bit Reset2 Flag BitVbus Flag Bit SOF/EOP2 Flag BitMailbox Out Flag Bit SPI Registers Reset1 Flag BitDone1 Flag Bit SPI Registers Register Name AddressMaster Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable BitSCK Strobe Bit Byte Mode BitRead Enable Bit Fifo Init BitFifo Error Flag Bit Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Receive Bit Length BitsTransfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transmit Interrupt Clear BitReceive CRC Bit CRC Enable BitCRC Clear Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WUart Registers SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Register Name AddressBaud Select Bits Uart Enable BitScale Select Bit Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Descriptions Name Type Pin DiagramPin Descriptions GPIO19 General Purpose IO GPIO20 General Purpose IOA1 HPI A1 A0 HPI A0Operating Conditions Booster Power Input 2.7V toAbsolute Maximum Ratings Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing Read Pulse Width Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time Document # 38-08014 Rev. *GHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Ordering Code Package Type PB-Free Package DiagramOrdering Information Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History
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