Cypress CY7C67200 Power Savings and Reset Description, Power Savings Mode Description, Sleep

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CY7C67200

Minimum Hardware Requirements for Standalone Mode – Peripheral Only

Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only

 

 

 

 

 

EZ-OTG

 

 

 

 

 

 

CY7C67200

 

 

 

 

 

VReg

VCC, AVCC,

nRESET

Reset

 

 

 

 

Logic

 

 

 

 

 

BoostVCC

 

 

 

VBus

 

 

 

 

 

 

 

 

 

Standard-B

D+

 

 

DPlus

 

 

D-

 

 

DMinus

 

 

or Mini-B

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

SHIELD

 

 

 

 

 

 

 

Bootstrap Options

 

 

 

 

 

 

Vcc Vcc

 

 

 

 

 

 

10k

10k

 

 

 

 

 

 

 

GPIO[30]

SCL*

 

 

 

 

 

 

GPIO[31]

SDA*

 

 

 

 

 

 

 

Int. 16k x8

 

 

 

 

 

 

Code / Data

 

 

 

 

VCC

Bootloading Firmware

 

 

 

 

 

 

 

 

 

A0 Up to 64k x8

VCC

 

 

 

 

A1

EEPROM

WP

 

 

 

 

A2

 

 

SCL

 

Reserved

 

 

GND

 

 

SDA

 

 

22pf

 

 

 

 

XIN

 

 

 

 

 

GND, AGND,

 

 

 

 

 

 

 

12MHz

 

 

 

 

 

BoostGND

XOUT

 

 

 

 

 

 

 

22pf

 

 

 

 

 

 

 

*Bootloading begins after POR + 3ms BIOS bootup

 

* Parallel Resonant

*GPIO[31:30]

31

30

 

 

 

Fundamental Mode

 

 

 

500uW

Up to 2k x8

 

SCL

SDA

 

 

 

 

 

 

 

20-33pf ±5%

>2k x8 to 64k x8

SDA

SCL

 

 

 

 

 

 

 

Power Savings and Reset Description

The EZ-OTG modes and reset conditions are described in this section.

Power Savings Mode Description

EZ-OTG has one main power savings mode, Sleep. For detailed information on Sleep mode; See section “Sleep”.

Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.

In addition, EZ-OTG is capable of slowing down the CPU clock speed through the CPU Speed register [0xC008] without affecting other peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz reduces the overall current draw by around 8 mA while reducing it from 48 MHz to 3 MHz reduces the overall current draw by approximately 15 mA.

Sleep

Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep Enable (bit 1) of the Power Control register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are true:

•GPIO pins maintain their configuration during sleep (in suspend).

•External Memory Address pins are driven low.

•XTALOUT is turned off.

•Internal PLL is turned off.

•Firmware must disable the charge pump (OTG Control register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS will only drop to VCC – (2 schottky diode drops).

•Booster circuit is turned off.

•USB transceivers is turned off.

•CPU suspends until a programmable wakeup event.

Document #: 38-08014 Rev. *G

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Contents EZ-OTG Features Typical ApplicationsCY7C67200 CY16Interface Descriptions IntroductionProcessor Core Functional Overview USB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberUSB Interface OTG InterfaceI2C Eeprom Interface Pins Pin Name Pin Number SPI Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral InterfaceHPI Interface Pins 1 Pin Name Pin Number Host Port Interface HPIHPI Addressing HPI A10 Charge Pump InterfaceCrystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Crystal Pins Pin Name Pin Number Boot Configuration InterfaceBoot Mode PinSleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Bank Register 0xC002 R/W Bank Register Example Hex Value Binary ValueReserved Hardware Revision Register 0xC004 RCPU Speed Register 0xC008 R/W CPU Speed Definition Processor SpeedHost/Device 2 Wake Enable Bit Host/Device 1 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable BitHalt Enable Bit OTG Interrupt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable BitUart Interrupt Enable Bit Gpio Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable BitPort 2A Diagnostic Enable Bit Port 1A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable BitTimeout Flag Bit Lock Enable BitWDT Enable Bit Reset Strobe BitTimer n Register R/W General USB RegistersUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AAMode Select Bit Port a Resistors Enable BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select EnablePreamble Enable Bit Sync Enable BitISO Enable Bit Arm Enable BitHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Error Flag Bit Underflow Flag BitStall Flag Bit NAK Flag BitACK Flag Bit Host n PID Register WPID Select Definition PID SelectHost n Count Result Register R Host n Device Address Register WVbus Interrupt Enable Bit ID Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable BitVbus Interrupt Flag Bit ID Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag BitHost n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration Host n Frame Register R USB Device Only Registers ReservedUSB Device Only Registers Register Name Address Device 1/DeviceIN/OUT Ignore Enable Bit Stall Enable BitNAK Interrupt Enable Bit Enable BitDevice n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WDevice n Endpoint n Status Register R/W OUT Exception Flag BitSetup Flag Bit Timeout occurred Timeout condition did not occurError occurred Error did not occur Exception Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result RegisterDevice n Interrupt Enable Register R/W SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable BitEP5 Interrupt Enable Bit EP2 Interrupt Enable Bit EP4 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable BitDevice n Address Register W Device n Status Register R/WReset Interrupt Flag Bit EP7 Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag BitSOF/EOP Timeout Flag Bit SOF/EOP Timeout Interrupt Counter BitsDevice n Frame Number Register R Device n SOF/EOP Count Register WVbus Pull-up Enable Bit Receive Disable BitCharge Pump Enable Bit Vbus Discharge Enable BitWrite Protect Enable Bit SAS Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag BitHSS Enable Bit SPI Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select BitGpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers Xoff Enable Bit CTS Enable BitReceive Interrupt Enable Bit RTS Polarity Select BitPacket Mode Select Bit Transmit Ready BitReceive Overflow Flag Bit Receive Packet Ready Flag BitHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WHSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WHPI Registers HPI Registers Register Name AddressVbus to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 RSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable BitSIEXmsg Register W SIE1msg Register SIE2msg RegisterData Bits HPI Mailbox Register 0xC0C6 R/WReset2 Flag Bit Vbus Flag BitID Flag Bit SOF/EOP2 Flag BitSPI Registers Reset1 Flag Bit Done1 Flag BitMailbox Out Flag Bit SPI Registers Register Name Address3Wire Enable Bit Phase Select BitMaster Active Enable Bit Master Enable BitByte Mode Bit Read Enable BitSCK Strobe Bit Fifo Init BitTransmit Interrupt Enable Bit Transfer Interrupt Enable BitFifo Error Flag Bit Receive Bit Length BitsCRC Mode Definition CRCMode CRC Polynomial Transmit Interrupt Flag BitTransfer Interrupt Flag Bit Transmit Interrupt Clear BitCRC Enable Bit CRC Clear BitReceive CRC Bit One in CRC BitSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WSPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WUart Registers Uart Registers Register Name AddressUart Enable Bit Scale Select BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 =Transmit Full Bit Uart Data Register 0xC0E4 R/WPin Descriptions Name Type Pin DiagramPin Descriptions GPIO20 General Purpose IO A1 HPI A1GPIO19 General Purpose IO A0 HPI A0Booster Power Input 2.7V to Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XtaloutDC Characteristics AC Timing Characteristics Reset TimingParameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing Data Access Time, from HPInRD falling HPI Host Port Interface Read Cycle TimingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *GHSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hardware CTS/RTS Handshake Hssrts HssctsRegister Summary Register SummaryGPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Package Diagram Ordering InformationOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48Issue Orig. Description of Change Date Document History
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