Analog Devices ADSP-TS201S manuals

Analog Devices ADSP-TS201S Specifications

48 pages1.61 Mb

a
- TigerSHARC
- Embedded Processor ADSP-TS201S
  - KEY FEATURES
  - KEY BENEFITS
- T
  - 2ADSP-TS201S
    - TABLE OF CONTENTS
      - REVISION HISTORY
    - 3GENERAL DESCRIPTION
      - 4DUAL COMPUTE BLOCKS
      - DATA ALIGNMENT BUFFER (DAB)
      - DUAL INTEGER ALU (IALU)
      - 5PROGRAM SEQUENCER
        Interrupt Controller
        Flexible Instruction Set
      - DSP MEMORY
      - 6EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
        Host Interface
        Multiprocessor Interface
        SDRAM Controller
        EPROM Interface
      - 7DMA CONTROLLER
        Rev. C | Page 8 of 48 | December 2006
        8Figure 4. ADSP-TS201S Shared Memory Multiprocessing System
      - 9LINK PORTS (LVDS)
      - TIMER AND GENERAL-PURPOSE I/O
      - RESET AND BOOTING
      - CLOCK DOMAINS
      - 10POWER DOMAI NS
      - FILTERING REFERENCE VOLTAGE AND CLOCKS
      - DEVELOPMENT TOOLS
      - 11EVALUATION KIT
      - DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)
      - ADDITIONAL INFORMATION
    - 12PIN FUNCTION DESCRIPTIONS
      - 13Table 5. Pin DefinitionsExternal Port Bus Controls
      - 14Table 6. Pin DefinitionsExternal Port Arbitration
      - 15Table 7. Pin DefinitionsExternal Port DMA/Flyby
      - 16Table 8. Pin DefinitionsExternal Port SDRA M Controller
      - 17Table 9. Pin DefinitionsJTAG Port
      - Table 10. Pin DefinitionsFlags, Interrupts, and Timer
      - 18Table 11. Pin DefinitionsLink Ports
      - Table 12. Pin DefinitionsImpedance Control, Drive Strength Control, and Regulator Enable
      - 19Table 13. Impedance Control Selection
      - Table 14. Drive Strength/Output Impedance Selection
      - Table 15. Pin DefinitionsPower, Ground, and Reference
  - 20ADSP-TS201S
    - STRAP PIN FUNCTION DESCRIPTIONS
    - 21ADSP-TS201SSPECIFICATIONS
      - OPERATING CONDITIONS
      - 22ELECTRICAL CHARACTERISTICS
        Table 18. Maximum Duty Cycle for Input Transient Voltage
      - PACKAGE INFORMATION
      - T
        ABSOLUTE MAXIMUM RATINGS
        ESD SENSITIVITY
    - 23a
      - 24TIMING SPECIFICATIONS
        General AC Timing
        25Table 23. Reference ClocksSystem Clock (SCLK) Cycle Time
        Table 24. Reference ClocksJTAG Test Clock (TCK) Cycle Time
        26Table 25. Power-Up Timing
        Table 26. Power-Up Reset Timing
        27Table 27. Normal Reset Timing
        Table 28. On-Chip DRAM Refresh
        28Table 29. AC Signal Specifications
        29Table 29. AC Signal Specifications (Continued)
        30Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing
        Table 31. Link Port LVDS Receive Electrical Characteristics
        32Figure 18. Link PortsOutput Clock
        LxCLKOUT
        LxBCMPO
        t
        Figure 21. Link PortsTransmission Start
        These parameters are valid for both clock edges.
        Figure 20. Link PortsData Output Setup and Hold
        V
        tREO tFEO
        VOD=0V
        - |
        t
        Figure 19. Link PortsDifferential Output Signals Transition Time
        VOD=0V
        t
        +|VOD|MIN
        V RLCL
        C C
        RL=100 CL=0.1pF CL_P=5pF CL_N=5pF
        LxCLKOUT
        LxDATO VOD=0V
        VOD=0V
        t LDOS t LDOH t LDOS t
        LxCLKOUT
        LxDATO VOD=0V
        VOD=0V
        t
        LxACKI
        33Figure 22. Link PortsTransmission End and Stops
        t
        t
        Figure 23. Link PortsBack to Back Transmission
        t
        LxBCMPO
        t
        t
        35Figure 25. Link PortsData Input Setup and Hold
        t
        t LDIS t LDIH t LDIS t
        These parameters are valid for both clock edges.
      - 36OUTPUT DRIVE CURRENTS
        VDD_IO=2.63V,40C
        VDD_IO=2.5V,+25C
        VDD_IO=2.38V,+105C
        I
        VDD_IO= 2.63V, 40C
        VDD_IO=2.5V,+25C
        70
        60
        40
        30
        20
        0
        10
        02.80.4 0.8 1.2 1.6 2.0 2.4
        Figure 30. Typical Drive Currents at Strength 4
        30
        VDD_IO=2.5V,+25C
        VDD_IO= 2.38V, +105C
        I
        VDD_IO= 2.63V, 40C
        VDD_IO=2.5V,+25C
        30
        25
        20
        15
        10
        0
        5
        OUTPUTPINCURRENT(mA)
        02.80.4 0.8 1.2 1.6 2.0 2.4
        OUTPUT PIN VOLTAGE (V)
        VDD_IO=2.5V,+25C
        VDD_IO=2.38V,+105C
        I
        VDD_IO= 2.63V, 40C
        VDD_IO=2.5V,+25C
        15.0
        12.5
        10.0
        7.5
        5.0
        0
        2.5
        OUTPUTPINCURRENT(mA)
        02.80.4 0.8 1.2 1.6 2.0 2.4
        OUTPUT PIN VOLTAGE (V)
        Figure 27. Typical Drive Currents at Strength 1
        Figure 26. Typical Drive Currents at Strength 0
        2.5 VDD_IO= 2.38V, +105C 5.0 7.5 10.0 12.5 15.0
        STRENGTH 0
        I
        VDD_IO=2.63V,40C
        5 VDD_IO= 2.38V, +105C 10 15 20 25
        STRENGTH1
        I
        VDD_IO= 2.63V, 40C
        Figure 28. Typical Drive Currents at Strength 2
        Figure 29. Typical Drive Currents at Strength 3
        OUTPUT PIN VOLTAGE (V)
        10 VDD_IO= 2.38V, +105C 20 30 40 60
        STRENGTH 4
        I
        50
        50 70
      - 37TEST CONDITIONS
        t
        tDECAY CLV()IL
        Figure 35. Output Enable/Disable
        90
        80
        70
        60
        VDD_IO=2.63V,40C
        VDD_IO=2.5V,+25C
        VDD_IO= 2.38V, +105C
        I
        VDD_IO= 2.63V, 40C
        VDD_IO=2.5V,+25C
        110
        50
        40
        30
        20
        0
        10
        OUTPUTPINCURRENT(mA)
        02.80.4 0.8 1.2 1.6 2.0 2.4
        Figure 33. Typical Drive Currents at Strength 7
        , and with V equal to 0.4 V.
        DECAY
        MEASURED_DIS
        DECAY
        MEASURED_DIS
        DIS
        Output Disable Time
        and the load current, I
        . This decay time can be approximated by the fol- lowing equation: The output disable time t
        is the difference between t
        and t
        as shown in Figure 35. The time t
        is calculated with test loads C
        and I
        Figure 31. Typical Drive Currents at Strength 5
        Figure 32. Typical Drive Currents at Strength 6
        OUTPUT PIN VOLTAGE (V)
        10 VDD_IO= 2.38V, +105C 20 30 40 50 110
        STRENGTH 7
        I
        100
        60 70 80 90 100
        Figure 34. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
        =
        REFERENCE SIGNAL
        t
        OUTPUTSTARTS DRIVING
        VOH(MEASURED) V VOL(MEASURED) +V
        t
        V V
        1.65V 0.85V
        HIGHIMPEDANCE S TATE. TESTCONDITIONS CAUS E THIS VOLTAGETO BEAPPROXIMATELY 1.25V.
        OUTPUTSTOPS DRIVING
        38Output Enable Time
        Capacitive Loading
        39Figure 41. Typical Output Rise and Fall Time (10% to 90%, V
        25
        LOADCAPACITANCE ( pF)
        10
        5
        0
        0102030405060708090100
        x
        20
        15
        10
        5
        0
        010 20 30 40 50 60 70 80 90 100
        LOADCAPACITANCE (pF)
        Y= 0.0573x + 0.9789
        20
        15
        10
        =2.5V) vs. Load Capacitance at Strength4
        Figure 42. Typical Output Rise and Fall Time (10% to 90%, V
        =2.5V) vs. Load Capacitance at Strength5
        Figure 43. Typical Output Rise and Fall Time (10% to 90%, V
        =2.5V) vs. Load Capacitance at Strength6
        RISEANDFALLTIMES(ns)
        5
        0
        010 20 30 40 50 60 70 80 90 100
        LOADCAPACITANCE (pF )
        STRENGTH 4 (VDD_IO=2.5V
        RISETIME
        FALLTI ME Y= 0.0592x + 1.0629
        RISEANDFALLTIMES(ns)
        25
        FALLTIME Y= 0.0493x + 0.8389
        STRENGTH5 (VDD_IO=2.5V)
        Figure 44. Typical Output Rise and Fall Time (10% to 90%, V
        =2.5V) vs. Load Capacitance at Strength7
        Figure 45. Typical Output Valid (V
        =2.5 V) vs. Load Capacitance at Max Case Temperature and Strength 0 to 7
        15
        OUTPUTVALID(ns)
        1 2 3 4 5 6 7
        STRENGTH07 (VDD_IO=2.5V) 0
      - 40ENVIRONMENTAL CONDITIONS
        Thermal Characteristics
      - 41576-BALL BGA_ED PIN CONFIGURATIONS
        Figure 46. 576-Ball BGA_ED Pin Configurations
        (Top View, Summary)
        42Table 35. 576-Ball (25 mm 25 mm) BGA_ED Ball Assignments
        44Table 35. 576-Ball (25 mm 25 mm) BGA_ED Ball Assignments (Continued)
      - 45OUTLINE DIMENSIONS
        Nonsolder Mask Defined (NSMD) 0.69 mm diameter 0.56 mm diameter
        TOP VIEW BOTTOMVIEW
        DETAILA
        Figure 47. 576-Ball BGA_ED (BP-576)
        SURFACE MOUNT DESIGN
        Table 36. BGA Data for Use with Surface Mount Design
        Package Ball Attach Type Solder Mask Opening Ball Pad Size 576-Ball BGA_ED (BP-576)
        46ORDERING GUIDE