Analog Devices ADSP-TS201S specifications Pin Definitions-Flags, Interrupts, and Timer

						ADSP-TS201S
Table 9. Pin Definitions—JTAG Port
	Signal	Type	Term	Description
		O/OD	nc1	Emulation. Connected to the DSP’s JTAG emulator target board connector only.
	EMU
	TCK	I	epd or epu1	Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
	TDI	I (pu_ad)	nc1	Test Data Input (JTAG). A serial data input of the scan path.
	TDO	O/T	nc1	Test Data Output (JTAG). A serial data output of the scan path.
	TMS	I (pu_ad)	nc1	Test Mode Select (JTAG). Used to control the test state machine.
		I/A (pu_ad)	na	Test Reset (JTAG). Resets the test state machine.		must be asserted or pulsed low
	TRST				TRST
				after power up for proper device operation. For more information, see Reset and
				Booting on Page 9.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

1See the reference on Page 11 to the JTAG emulation technical reference EE-68.

Table 10. Pin Definitions—Flags, Interrupts, and Timer

Signal	Type	Term	Description
FLAG3–0	I/O/A	nc	FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin
	(pu)		can be configured individually for input or for output. FLAG3–0 are inputs after power-up
			and reset.
	I/A	nc	Interrupt Request. When asserted, the DSP generates an interrupt. Each of the				pins
IRQ3–0						IRQ3–0
	(pu)		can be independently set for edge-triggered or level-sensitive operation. After reset, these
			pins are disabled unless the		strap option and interrupt vectors are initialized for
				IRQ3–0
			booting.
TMR0E	O	na	Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.
			For more information, see Table 16 on Page 20.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Rev. C Page 17 of 48 December 2006