Vod, Vid | Analog Devices ADSP-TS201S manual

ADSP-TS201S

Link Port Low Voltage, Differential-Signal (LVDS)

Electrical Characteristics, and Timing

Table 30 and Table 31 with Figure 16 provide the electrical characteristics for the LVDS link ports. The LVDS link port sig- nal definitions represent all differential signals with a VOD = 0 V level and use signal naming without N (negative) and P (posi- tive) suffixes (see Figure 17).

Table 30. Link Port LVDS Transmit Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

VOH

Output Voltage High, VO_P or VO_N

RL = 100 Ω

1.85

V

VOL

Output Voltage Low, VO_P or VO_N

RL = 100 Ω

0.92

V

VOD

Output Differential Voltage

RL = 100 Ω

300

650

mV

IOS

Short-Circuit Output Current

VO_P or VO_N = 0 V

+5/– 55

mA

VOD = 0 V

±10

mA

VOCM

Common-Mode Output Voltage

1.20

1.50

V

Table 31. Link Port LVDS Receive Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

VID

Differential Input Voltage

tLDIS/tLDIH ≥ 0.20 ns

250

850

mV

tLDIS/tLDIH ≥ 0.25 ns

217

850

mV

tLDIS/tLDIH ≥ 0.30 ns

206

850

mV

tLDIS/tLDIH ≥ 0.35 ns

195

850

mV

VICM

Common-Mode Input Voltage

0.6

1.57

V

VO_P

VOD

= (VO_P – VO_N)

RL

(V

O_P

+ V

)

VOCM =

O_N

VO_N

2

Figure 16. Link Ports—Transmit Electrical Characteristics

DIFFERENTIAL PAIR WAVEFORMS

Lx<PIN>P

VO_N

Lx<PIN>N

VO_P

DIFFERENTIAL VOLTAGE WAVEFORM

Lx<PIN>

VOD = 0V

VOD = VO_P – VO_N

Figure 17. Link Ports—Signals Definition

Rev. C Page 30 of 48 December 2006

Image 30

Analog Devices ADSP-TS201S specifications Link Port Lvds Transmit Electrical Characteristics, Vod, Vid

Contents

ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 ns Dual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Interrupt Controller Program SequencerDSP Memory Flexible Instruction Set External Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal Space Multiprocessor Interface DMA ControllerHost Interface Sdram Controller DMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports Lvds Power Domains Filtering Reference Voltage and ClocksDevelopment Tools Evaluation KIT Additional Information Sclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description Ratio Pin Definitions-External Port Bus Controls ACK T/OD Signal Type Pin Definitions-External Port Arbitration Sample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Makes Hdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10 Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term Description CONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1 DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control Selection Pin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Operating Conditions Sclkvref Maximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2 Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand Information General AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max Unit Power-Up Timing1 Power-Up Reset Timing Normal Reset Timing On-Chip Dram Refresh1 AC Signal Specifications OutputDisable Max Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9 Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VOD Link Port-Data Out Timing Parameter Description Min Max Unit Link Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold Figure Link Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at Strength Output Disable Time Test Conditions Output Enable Time Capacitive Loading Times Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical Unit Ball Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball Assignments L0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3N DS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINN Package Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December