Analog Devices ADSP-TS201S OUTPUT DRIVE CURRENTS

Rev. C | Page 36 of 48 | December 2006

ADSP-TS201S

OUTPUT DRIVE CURRENTS

Figure 26 through Figure 33 show typical I–V characteristics for

the output drivers of the ADSP-TS201S processor. The curves in

these diagrams represent the current drive capability of the out-

put drivers as a function of output voltage over the range of

drive strengths. Typical drive currents for intermediate temper-

atures (such as 85°C) should be obtained from the curves using

linear interpolation. For complete output driver characteristics,

refer to the DSP’s IBIS models, available on the Analog Devices

website (www.analog.com).

Figure 26. Typical Drive Currents at Strength 0

Figure 27. Typical Drive Currents at Strength 1

OUTPUT PIN VOLTAGE (V)02.80.4 0.8 1.2 1.6 2.0 2.4OUTPUTPINCURRENT(mA)–2.502.5VDD_IO= 2.38V, +105°C–5.0–7.5–10.0–12.5–15.05.07.510.012.515.0STRENGTH 0VDD_IO=2.5V,+25°CVDD_IO= 2.63V, –40°C

IOL

IOH

VDD_IO=2.38V,+105°CVDD_IO=2.5V,+25°CVDD_IO=2.63V,–40°C

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

OUTPUTPINCURRENT(mA)

–5

0

5

VDD_IO= 2.38V, +105°C

–10

–15

–20

–25

10

15

20

25

30

STRENGTH1

VDD_IO=2.5V,+25°C

VDD_IO= 2.63V, –40°C

IOL

IOH

VDD_IO= 2.38V, +105°C

VDD_IO=2.5V,+25°C

VDD_IO= 2.63V, –40°C

–30

Figure 28. Typical Drive Currents at Strength 2

Figure 29. Typical Drive Currents at Strength 3

Figure 30. Typical Drive Currents at Strength 4

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

OUTPUTPINCURRENT(mA)

–9

0

9

VDD_IO= 2.38V, +105°C

–18

–27

–36

–45

18

36

45

STRENGTH 2

VDD_IO= 2.5V, +25°C VDD_IO = 2.63V,–40°C

IOL

IOH

VDD_IO= 2.38V, +105°C

VDD_IO= 2.5V, +25°C

VDD_IO= 2.63V, –40°C

27

OUTPUT PIN VOLTAGE (V)

02.80.4 0.8 1.2 1.6 2.0 2.4

OUTPUTPINCURRENT(mA)

–11

0

11

VDD_IO= 2.38V, +105°C

–22

–33

–44

–55

22

33

44

55

STRENGTH 3

VDD_IO=2.5V,+25°C

VDD_IO= 2.63V, –40°C

IOL

IOH

VDD_IO= 2.38V, +105°C

VDD_IO=2.5V,+25°C

VDD_IO= 2.63V, –40°C

OUTPUT PIN VOLTAGE (V)02.80.4 0.8 1.2 1.6 2.0 2.4

OUTPUTPINCURRENT(mA)

–10010VDD_IO= 2.38V, +105°C–20–30–40–602030406070STRENGTH 4VDD_IO=2.5V,+25°CVDD_IO= 2.63V, –40°C

IOL

IOH

VDD_IO=2.38V,+105°CVDD_IO=2.5V,+25°CVDD_IO=2.63V,–40°C50–50–70

Contents

Main a TigerSHARC Embedded Processor ADSP-TS201S KEY FEATURES KEY BENEFITS ADSP-TS201S TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION DUAL COMPUTE BLOCKS DATA ALIGNMENT BUFFER (DAB) DUAL INTEGER ALU (IALU) PROGRAM SEQUENCER Interrupt Controller Flexible Instruction Set DSP MEMORY EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA CONTROLLER Rev. C | Page 8 of 48 | December 2006 Figure 4. ADSP-TS201S Shared Memory Multiprocessing System LINK PORTS (LVDS) TIMER AND GENERAL-PURPOSE I/O RESET AND BOOTING CLOCK DOMAINS POWER DOMAI NS FILTERING REFERENCE VOLTAGE AND CLOCKS DEVELOPMENT TOOLS EVALUATION KIT DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) ADDITIONAL INFORMATION PIN FUNCTION DESCRIPTIONS Table 5. Pin DefinitionsExternal Port Bus Controls Table 6. Pin DefinitionsExternal Port Arbitration Table 7. Pin DefinitionsExternal Port DMA/Flyby Table 8. Pin DefinitionsExternal Port SDRA M Controller Table 9. Pin DefinitionsJTAG Port Table 10. Pin DefinitionsFlags, Interrupts, and Timer Table 11. Pin DefinitionsLink Ports Table 12. Pin DefinitionsImpedance Control, Drive Strength Control, and Regulator Enable Table 13. Impedance Control Selection Table 14. Drive Strength/Output Impedance Selection Table 15. Pin DefinitionsPower, Ground, and Reference ADSP-TS201S STRAP PIN FUNCTION DESCRIPTIONS ADSP-TS201SSPECIFICATIONS OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS Table 18. Maximum Duty Cycle for Input Transient Voltage PACKAGE INFORMATION T ABSOLUTE MAXIMUM RATINGS a TIMING SPECIFICATIONS General AC Timing Table 23. Reference ClocksSystem Clock (SCLK) Cycle Time Table 24. Reference ClocksJTAG Test Clock (TCK) Cycle Time Table 25. Power-Up Timing Table 26. Power-Up Reset Timing Table 27. Normal Reset Timing Table 28. On-Chip DRAM Refresh Table 29. AC Signal Specifications Table 29. AC Signal Specifications (Continued) Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing Table 31. Link Port LVDS Receive Electrical Characteristics Page Figure 18. Link PortsOutput Clock LxCLKOUT LxBCMPO t Figure 21. Link PortsTransmission Start Figure 22. Link PortsTransmission End and Stops t t Figure 23. Link PortsBack to Back Transmission t Page Figure 25. Link PortsData Input Setup and Hold t t LDIS t LDIH t LDIS t These parameters are valid for both clock edges. OUTPUT DRIVE CURRENTS VDD_IO=2.63V,40C VDD_IO=2.5V,+25C VDD_IO=2.38V,+105C I TEST CONDITIONS t tDECAY CLV()IL Figure 35. Output Enable/Disable 90 Output Enable Time Capacitive Loading Figure 41. Typical Output Rise and Fall Time (10% to 90%, V 25 LOADCAPACITANCE ( pF) 10 5 ENVIRONMENTAL CONDITIONS Thermal Characteristics 576-BALL BGA_ED PIN CONFIGURATIONS Figure 46. 576-Ball BGA_ED Pin Configurations (Top View, Summary) Table 35. 576-Ball (25 mm 25 mm) BGA_ED Ball Assignments Page Table 35. 576-Ball (25 mm 25 mm) BGA_ED Ball Assignments (Continued) OUTLINE DIMENSIONS Nonsolder Mask Defined (NSMD) 0.69 mm diameter 0.56 mm diameter TOP VIEW BOTTOMVIEW DETAILA Figure 47. 576-Ball BGA_ED (BP-576) ORDERING GUIDE