ADSP-TS201S

TABLE OF CONTENTS

 

General Description

3

Dual Compute Blocks

4

Data Alignment Buffer (DAB)

4

Dual Integer ALU (IALU)

4

Program Sequencer

5

Interrupt Controller

5

Flexible Instruction Set

5

DSP Memory

5

External Port (Off-Chip Memory/Peripherals

 

Interface)

6

Host Interface

7

Multiprocessor Interface

7

SDRAM Controller

7

EPROM Interface

7

DMA Controller

7

Link Ports (LVDS)

9

Timer and General-Purpose I/O

9

Reset and Booting

9

Clock Domains

9

Power Domains

10

Filtering Reference Voltage and Clocks

10

Development Tools

10

Evaluation Kit

11

Designing an Emulator-Compatible

 

DSP Board (Target)

11

Additional Information

11

Pin Function Descriptions

12

Strap Pin Function Descriptions

20

ADSP-TS201S—Specifications

21

Operating Conditions

21

Electrical Characteristics

22

Package Information

23

Absolute Maximum Ratings

23

ESD Sensitivity

23

Timing Specifications

24

General AC Timing

24

Link Port Low Voltage, Differential-Signal (LVDS)

 

Electrical Characteristics, and Timing

30

Link Port—Data Out Timing

31

Link Port—Data In Timing

34

Output Drive Currents

36

Test Conditions

37

Output Disable Time

37

Output Enable Time

38

Capacitive Loading

38

Environmental Conditions

40

Thermal Characteristics

40

576-Ball BGA_ED Pin Configurations

41

Outline Dimensions

45

Surface Mount Design

45

Ordering Guide

46

REVISION HISTORY

 

12/06—Rev. B to Rev. C

 

Applied Corrections to:

 

Figure 7, SCLK_VREF Filtering Scheme

10

Operating Conditions

21

Added On-Chip DRAM Refresh

27

Ordering Guide

46

Rev. C Page 2 of 48 December 2006

Page 2
Image 2
Analog Devices ADSP-TS201S specifications