Link Port-Data In Timing | Analog Devices ADSP-TS201S guide

ADSP-TS201S

Link Port—Data In Timing

Table 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS link ports.

Table 33. Link Port—Data In Timing

Parameter	Description	Min	Max	Unit
Inputs
tLCLKIP	LxCLKIN Period (Figure 25)	Greater of 1.8
		1	12.5	ns
		or 0.9 × tCCLK	12.5	ns
tLDIS	LxDATI Input Setup (Figure 25)	0.201, 2		ns
		0.251, 3		ns
		0.301, 4		ns
		0.351, 5		ns
tLDIH	LxDATI Input Hold (Figure 25)	0.201, 2		ns
		0.251, 3		ns
		0.301, 4		ns
		0.351, 5		ns
tBCMPIS		1
	LxBCMPI Setup (Figure 24)	1		ns
	LxBCMPI Setup (Figure 24)	2 × tLCLKIP		ns
tBCMPIH		1
	LxBCMPI Hold (Figure 24)	1		ns
	LxBCMPI Hold (Figure 24)	2 × tLCLKIP		ns

1Timing is relative to the 0 differential voltage (VOD = 0).

2 VID = 250 mV

3 VID = 217 mV

4 VID = 206 mV

5 VID = 195 mV

FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD

LxCLKIN

VOD = 0V

LxDATI

VOD = 0V

tBCMPIS

tBCMPIH

LxBCMPI

Figure 24. Link Ports—Last Received Quad Word

Rev. C Page 34 of 48 December 2006

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Image 34

Analog Devices ADSP-TS201S specifications Link Port-Data In Timing, LxBCMPI Hold Figure

Contents

ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 ns Data Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Interrupt Controller Program SequencerDSP Memory Flexible Instruction Set External Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal Space Multiprocessor Interface DMA ControllerHost Interface Sdram Controller DMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports Lvds Filtering Reference Voltage and Clocks Power DomainsDevelopment Tools Evaluation KIT Additional Information Sclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description Ratio Pin Definitions-External Port Bus Controls ACK T/OD Signal Type Pin Definitions-External Port Arbitration Sample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Makes Hdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10 Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term Description CONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1 DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control Selection Type at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Operating Conditions Sclkvref Maximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2 Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand Information General AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max Unit Power-Up Timing1 Power-Up Reset Timing Normal Reset Timing On-Chip Dram Refresh1 AC Signal Specifications OutputDisable Max Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9 Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VOD Link Port-Data Out Timing Parameter Description Min Max Unit Link Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold Figure Link Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at Strength Output Disable Time Test Conditions Output Enable Time Capacitive Loading Times Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical Unit Ball Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball Assignments L0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3N DS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINN Package Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December

ADSP-TS201S

Link Port—Data In Timing

Parameter

LxBCMPI Hold (Figure 24)

Figure 24. Link Ports—Last Received Quad Word