ADSP-TS201S
Link Port—Data Out Timing
Table 32 with Figure 18, Figure 19, Figure 20, Figure 21,
Figure 22, and Figure 23 provide the data out timing for the
LVDS link ports.
Table 32. Link
Parameter |
| Description | Min |
| Max | Unit | |
Outputs |
|
|
|
|
|
|
|
tREO |
| Rising Edge (Figure 19) |
|
| 350 | ps | |
tFEO |
| Falling Edge (Figure 19) |
|
| 350 | ps | |
tLCLKOP |
| LxCLKOUT Period (Figure 18) | Greater of 2.0 or |
| Smaller of 12.5 or |
| |
|
|
|
| 0.9 ⋅ LCR ⋅ tCCLK1, 2, 3 |
| 1.1 ⋅ LCR ⋅ tCCLK1, 2, 3 | ns |
tLCLKOH |
| LxCLKOUT High (Figure 18) | 1 |
| 1 | ns | |
| 0.4 ⋅ tLCLKOP |
| 0.6 ⋅ tLCLKOP | ||||
tLCLKOL |
| LxCLKOUT Low (Figure 18) | 1 |
| 1 | ns | |
| 0.4 ⋅ tLCLKOP |
| 0.6 ⋅ tLCLKOP | ||||
tCOJT |
| LxCLKOUT Jitter (Figure 18) |
|
| ±1504, 5, 6 | ps | |
|
|
|
|
|
| ±2507 | ps |
tLDOS |
| LxDATO Output Setup (Figure 20) |
| 1, 4, | 8 | ns | |
| 0.25 ⋅ LCR ⋅ tCCLK – 0.10 ⋅ tCCLK |
| |||||
|
|
|
|
| 1, 5, 6, 8 | ns | |
|
|
|
| 0.25 ⋅ LCR ⋅ tCCLK – 0.15 ⋅ tCCLK |
| ||
|
|
|
| 0.25 ⋅ LCR ⋅ tCCLK – 0.30 ⋅ | 1, | 7, 8 | ns |
|
|
|
| tCCLK |
| ||
tLDOH |
| LxDATO Output Hold (Figure 20) |
| 1, 4, 8 | ns | ||
| 0.25 ⋅ LCR ⋅ tCCLK – 0.10 ⋅ tCCLK |
| |||||
|
|
|
|
| 1, 5, 6, 8 | ns | |
|
|
|
| 0.25 ⋅ LCR ⋅ tCCLK – 0.15 ⋅ tCCLK |
| ||
|
|
|
| 0.25 ⋅ LCR ⋅ tCCLK – 0.30 ⋅ | 1, 7, 8 | ns | |
|
|
|
| tCCLK |
| ||
tLACKID |
| Delay from LxACKI rising edge to first transmission |
|
| 1, 2 | ns | |
|
|
| 16 ⋅ LCR ⋅ tCCLK | ||||
|
| clock edge (Figure 21) |
|
|
|
| |
tBCMPOV |
|
|
|
|
| 1, 2 |
|
| LxBCMPO Valid (Figure 21) |
|
| ns | |||
|
|
| 2 ⋅ LCR ⋅ tCCLK | ||||
tBCMPOH |
|
| Hold (Figure 22) | 3 ⋅ TSW – 0.51, 9 |
|
| ns |
LxBCMPO |
|
| |||||
Inputs |
|
|
|
|
|
|
|
tLACKIS |
| LxACKI low setup to guarantee that the transmitter |
|
|
|
| |
|
| stops transmitting (Figure 22) |
|
|
|
| |
|
| LxACKI high setup to guarantee that the transmitter |
|
|
|
| |
|
| continues its transmission without any interruption |
|
|
|
| |
|
| (Figure 23) | 1, 2 |
|
| ns | |
|
| 16 ⋅ LCR ⋅ tCCLK |
|
| |||
tLACKIH |
| LxACKI High Hold Time (Figure 23) | 0.51 |
|
| ns | |
1Timing is relative to the 0 differential voltage (VOD = 0).
2LCR (link port clock ratio) = 1, 1.5, 2, or 4. tCCLK is the core period.
3For the cases of tLCLKOP = 2.0 ns and tLCLKOP = 12.5 ns, the effect of tCOJT specification on output period must be considered.
4 LCR= 1.
5 LCR= 1.5.
6 LCR= 2.
7 LCR= 4.
8The tLDOS and tLDOH values include LCLKOUT jitter.
9TSW is a
Rev. C Page 31 of 48 December 2006
