Analog Devices ADSP-TS201S specifications

•	TigerSHARC®
a
	Embedded Processor
	ADSP-TS201S

KEY FEATURES

Up to 600 MHz, 1.67 ns instruction cycle rate

24M bits of internal—on-chip—DRAM memory

25 mm × 25 mm (576-ball) thermally enhanced ball grid array package

Dual-computation blocks—each containing an ALU, a multiplier, a shifter, a register file, and a communications logic unit (CLU)

Dual-integer ALUs, providing data addressing and pointer manipulation

Integrated I/O includes 14-channel DMA controller, external port, four link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

1149.1 IEEE-compliant JTAG test access port for on-chip emulation

Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats

KEY BENEFITS

Provides high performance static superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications

Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1)

Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs

Eases DSP programming through extremely flexible instruc- tion set and high-level-language-friendly DSP architecture

Enables scalable multiprocessing systems with low commu- nications overhead

Provides on-chip arbitration for glueless multiprocessing

DATA ADDRESS GENERATION 24M BITS INTERNAL MEMORY SOC BUS JTAG PORT

INTEGER

32

32

INTEGER

MEMORY BLOCKS

JTAG

6

J ALU

K ALU

(PAGE CACHE)

EXTERNAL

32-BIT × 32-BIT

32-BIT × 32-BIT

4 × CROSSBAR CONNECT

PROGRAM

PORT

SEQUENCER

A

D A D

A D A D

32

ADDR

J-BUS ADDR

32

HOST

ADDR

64

FETCH

MULTI-

DATA

J-BUS DATA

128

PROC

SDRAM

8

CTRL

K-BUS ADDR

32

CTRL

BTB

C-BUS

10

CTRL

K-BUS DATA

128

ARB

I-BUS ADDR

32

SOC

EXT DMA

I/F

128

REQ

4

PC

I-BUS DATA

DMA

S-BUS ADDR

21

LINK PORTS

T

4

IN

8

S-BUS DATA

128

L0

4

IAB

OUT

8

4

IN

8

L1

4

OUT

8

4

IN

8

128

128

L2

4

OUT

8

X

Y

4

IN

8

REGISTER

128

128

REGISTER

CLU

SHIFT

ALU MUL

MUL

ALU

SHIFT

CLU

L3

4

FILE

DAB

DAB

FILE

OUT

8

32-BIT × 32-BIT

32-BIT × 32-BIT

COMPUTATIONAL BLOCKS

Figure 1. Functional Block Diagram

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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