Analog Devices ADSP-TS201S Pin Definitions-Link Ports, CONTROLIMP0, CONTROLIMP1, DS1, Enedreg

ADSP-TS201S

Table 11. Pin Definitions—Link Ports

Signal	Type	Term	Description
LxDATO3–0P	O	nc	Link Ports 3–0 Data 3–0 Transmit LVDS P
LxDATO3–0N	O	nc	Link Ports 3–0 Data 3–0 Transmit LVDS N
LxCLKOUTP	O	nc	Link Ports 3–0 Transmit Clock LVDS P
LxCLKOUTN	O	nc	Link Ports 3–0 Transmit Clock LVDS N
LxACKI	I (pd)	nc	Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the
			transmitter that it may continue the transmission.
	O (pu)	nc	Link Ports 3–0 Block Completion. When the transmission is executed using DMA, this
LxBCMPO
			signal indicates to the receiver that the transmitted block is completed. The pull-up
			resistor is present on	L0BCMPO	only. At reset, the	L1BCMPO,	L2BCMPO,	and	L3BCMPO
			pins are strap pins. For more information, see Table 16 on Page 20.
LxDATI3–0P	I	VDD_IO	Link Ports 3–0 Data 3–0 Receive LVDS P
LxDATI3–0N	I	VDD_IO	Link Ports 3–0 Data 3–0 Receive LVDS N
LxCLKINP	I/A	VDD_IO	Link Ports 3–0 Receive Clock LVDS P
LxCLKINN	I/A	VDD_IO	Link Ports 3–0 Receive Clock LVDS N
LxACKO	O	nc	Link Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
			transmitter that it may continue the transmission.
	I (pd_l)	VSS	Link Ports 3–0 Block Completion. When the reception is executed using DMA, this
LxBCMPI
			signal indicates to the receiver that the transmitted block is completed.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ; pd_l = internal pull-down 50 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable

Signal	Type	Term	Description
CONTROLIMP0	I (pd)	na	Impedance Control. As shown in Table 13, the CONTROLIMP1–0 pins select between
CONTROLIMP1	I (pu)	na	normal driver mode and A/D driver mode. When using normal mode (recommended),
			the output drive strength is set relative to maximum drive strength according to
			Table 14. When using A/D mode, the resistance control operates in the analog mode,
			where drive strength is continuously controlled to match a specific line impedance as
			shown in Table 14.
DS2, 0	I (pu)	na	Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength calcu-
DS1	I (pd)		lation, see Output Drive Currents on Page 36. The drive strength for some pins is preset,
			not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%)
			include:			TDO,		and		The drive strength for the ACK pin is always
				CPA,	DPA,		EMU,		RST_OUT.
			x2 drive strength 7 (100%).
ENEDREG	I (pu)	VSS	Connect the ENEDREG pin to VSS. Connect the VDD_DRAM pins to a properly decoupled
			DRAM power supply.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Rev. C Page 18 of 48 December 2006