Rev. C | Page 6 of 48 | December 2006
ADSP-TS201S
33.6G bytes per second, enabling the core and I/O to access
eight 32-bit data-words and four 32-bit instructions each cycle.
The DSP’s flexible memory structure enables:
• DSP core and I/O accesses to different memory blocks in
the same cycle
• DSP core access to three memory blocks in parallel—one
instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS201S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4Gword
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G byte per
second over the external bus.
The external bus can be configured for 32-bit or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
Figure 3. ADSP-TS201S Memory Map
RESERVED
RESER V ED
INTERNALREGISTERS(UREGS)
INTERNALMEMORYBLOCK4
INTERNALMEMORYBLOCK 2
INTERNALMEMORYBLOCK 0
0x03FFFFFF
0x001E0000
0x001E0 3F F
0x000DFFFF
0x000C 0 000
0x0009FFFF
0x00080 00 0
0x0005FFFF
0x00040 00 0
0x0001FFFF
0x00000 00 0
INTERNALSPACE
PROCESSOR ID 7
PROCESSOR ID 6
PROCESSOR ID 5
PROCESSOR ID 4
PROCESSOR ID 3
PROCESSOR ID 2
PROCESSOR ID 1
PROCESSOR ID 0
BROADCAST
HOST(MSH)
BANK1 (MS 1)
BANK0 (MS 0)
MSSDBANK 0(MSSD0)
INTERNAL MEMORY
0x5000 00 00
0x40000 00 0
0x3800 00 00
0x30000 00 0
0x2C00 00 00
0x28000 00 0
0x24000 00 0
0x20000 00 0
0x1C00 00 00
0x18000 00 0
0x14000 00 0
0x10000 00 0
0x0C00 00 00
0x03FFF FF F
0x00000 00 0
GLOBALSPACE
0xFFFFFFFF
MULTIPROCESSORMEMORYSPACEEXTERNALMEMORYSPACE
EACHIS A COPY
OFINTERNALSPACE
RESERVED
INTERNALMEMORYBLOCK6
INTERNALMEMORYBLOCK 8
0x0011FFFF
0x00100 00 0
INTERNALMEMORYBLOCK10
0x0015FFFF
0x00140 00 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SOC RE GISTE RS(UREGS) 0x001F0000
0x001F0 3F F
MSSDBANK 1(MSSD1)
MSSDBANK2 (MSSD2)
MSSDBANK 3(MSSD3)
0x6000 00 00
0x7000 00 00
0x8000 00 00
RESERVED
RESERVED
RESERVED
RESERVED
0x5400 00 00
0x44000 00 0
0x6400 00 00
0x7400 00 00