Analog Devices ADSP-TS201S DS2-0 Static Pins-Must Be Constant, Strap SYS 9, Strap Pins

ADSP-TS201S

Table 29. AC Signal Specifications (Continued)

(All values in this table are in nanoseconds.)

Name	Description	SetupInput (Min)	HoldInput (Min)	OutputValid (Max)	OutputHold (Min)	OutputEnable (Min)	OutputDisable (Max)	Reference Clock
						1	1
DS2–08	Static Pins—Must Be Constant	—	—	—	—	—	—	—
SCLKRAT2–08	Static Pins—Must Be Constant	—	—	—	—	—	—	—
ENEDREG	Static Pins—Must Be Connected to VSS	—	—	—	—	—	—	—
STRAP SYS9, 10	Strap Pins	1.5	0.5	—	—	—	—	SCLK
JTAG SYS11, 12	JTAG System Pins	+2.5	+10.0	+12.0	–1.0	—	—	TCK

1The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.

2For input specifications on FLAG3–0 pins, see Table 21.

3These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.

4 For additional requirement details, see Reset and Booting on Page 9.

5 RST_IN clock reference is the falling edge of SCLK.

6 TDO output clock reference is the falling edge of TCK.

7 Reference clock depends on function.

8 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.

9 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.

10Specifications applicable during reset only.

11JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0, L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP, L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0, L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0, SCLKRAT2–0, DS2–0, ENEDREG.

12JTAG system output timing clock reference is the falling edge of TCK.

REFERENCE
CLOCK
1.25V	tSCLK OR tTCK
INPUT
SIGNAL
	1.25V	INPUT
		SETUP
OUTPUT
SIGNAL
OUTPUT	1.25V
VALID
THREE-
STATE
OUTPUT
DISABLE

INPUT

HOLD

OUTPUT

HOLD

OUTPUT ENABLE

Figure 15. General AC Parameters Timing

Rev. C Page 29 of 48 December 2006