Analog Devices ADSP-TS201S Pin Definitions-I/O Strap Pins, Type at Signal Reset, Pin Rstin =

ADSP-TS201S

STRAP PIN FUNCTION DESCRIPTIONS

Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value. If a strap pin is not connected to an over- driving external pull-up, pull-down, or logic load, the DSP samples the default value during reset. If strap pins are

Table 16. Pin Definitions—I/O Strap Pins

connected to logic inputs, a stronger external pull-up or pull- down may be required to ensure default value depending on leakage and/or low level input current of the logic load. To set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pull-up or pull-down. Table 16 lists and describes each of the DSP’s strap pins.

	Type (at
Signal	Reset)	On Pin …		Description
EBOOT	I			EPROM Boot.
			BMS
	(pd_0)			0	= boot from EPROM immediately after reset (default)
				1	= idle after reset and wait for an external device to boot DSP
					through the external port or a link port
IRQEN	I			Interrupt Enable.
			BM
	(pd)			0	= disable and set		IRQ3–0		interrupts to edge-sensitive after
					reset (default)
				1	= enable and set	IRQ3–0		interrupts to level-sensitive
					immediately after reset
LINK_DWIDTH	I		TMR0E	Link Port Input Default Data Width.
	(pd)			0	= 1-bit (default)
				1	= 4-bit
SYS_REG_WE	I			SYSCON and SDRCON Write Enable.
			BUSLOCK
	(pd_0)			0	= one-time writable after reset (default)
				1	= always writable
TM1	I			Test Mode 1. Do not overdrive default value during reset.
			L1BCMPO
	(pu)
TM2	I			Test Mode 2. Do not overdrive default value during reset.
			L2BCMPO
	(pu)
TM3	I			Test Mode 3. Do not overdrive default value during reset.
			L3BCMPO
	(pu)

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

When default configuration is used, no external resistor is needed on the strap pins. To apply other configurations, a

500 Ω resistor connected to VDD_IO is required. If providing external pull-downs, do not strap these pins directly to VSS; the strap pins require 500 Ω resistor straps.

All strap pins are sampled on the rising edge of RST_IN (deas- sertion edge). Each pin latches the strapped pin state (state of the strap pin at the rising edge of RST_IN). Shortly after deas- sertion of RST_IN, these pins are reconfigured to their normal functionality.

These strap pins have an internal pull-down resistor, pull-up resistor, or no-resistor (three-state) on each pin. The resistor type, which is connected to the I/O pad, depends on whether RST_IN is active (low) or if RST_IN is deasserted (high).

Table 17 shows the resistors that are enabled during active reset and during normal operation.

Table 17. Strap Pin Internal Resistors—Active Reset (RST_IN = 0) vs. Normal Operation (RST_IN = 1)

Pin	RST_IN = 0		RST_IN = 1
	(pd_0)	(pu_0)
BMS
	(pd)		Driven
BM
TMR0E	(pd)		Driven
	(pd_0)	(pu_0)
BUSLOCK
	(pu)		Driven
L1BCMPO
	(pu)		Driven
L2BCMPO
	(pu)		Driven
L3BCMPO

pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0;

pu_0 = internal pull-up 5 kΩ on DSP ID = 0

Rev. C Page 20 of 48 December 2006