Link Ports-Transmission End and Stops | Analog Devices ADSP-TS201S

ADSP-TS201S

FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD

LxCLKOUT

VOD = 0V

LxDATO

VOD = 0V

LxACKI

LxBCMPO

tLACKIS

tBCMPOH

LAST EDGE IN A QUAD WORD

tLACKIH

LxCLKOUT

VOD = 0V

LxDATO

VOD = 0V

LxACKI

Figure 22. Link Ports—Transmission End and Stops

LAST EDGE IN A QUAD WORD


		tLACKIS					tLACKIH

Figure 23. Link Ports—Back to Back Transmission

Rev. C Page 33 of 48 December 2006

Page 33

Image 33

Analog Devices ADSP-TS201S specifications Link Ports-Transmission End and Stops

Contents

ADSP-TS201S ADSP-TS201S Clock General-Purpose Algorithm Benchmarks at 600 MHzBenchmark Speed Cycles FIR filter per real tap 83 ns Dual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu DSP Memory Program SequencerInterrupt Controller Flexible Instruction Set Internal Space External Port OFF-CHIP MEMORY/PERIPHERALS Interface Host Interface DMA ControllerMultiprocessor Interface Sdram Controller DMA controller provides these additional features Reset and Booting Timer and GENERAL-PURPOSE I/ONo Boot, Run from Memory Addresses Link Ports Lvds Power Domains Filtering Reference Voltage and ClocksDevelopment Tools Additional Information Evaluation KIT Signal Type Term Description Pin Definitions-Clocks and ResetSclk Ratio Ratio ACK T/OD Pin Definitions-External Port Bus Controls Pin Definitions-External Port Arbitration Signal Type DSP performs DMA transfers according to the DMA Pin Definitions-External Port DMA/FlybySample the data instead of the TigerSHARC Makes Ldqm Pin Definitions-External Port Sdram ControllerHdqm SDA10 Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and Timer CONTROLIMP0 Pin Definitions-Link PortsCONTROLIMP1 DS1 Driver Mode Pin Definitions-Power, Ground, and ReferenceDS2-0 Drive Output Pins Strength Impedance Impedance Control Selection Pin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Sclkvref Operating Conditions Maximum Duty Cycle for Input Transient Voltage Electrical CharacteristicsMaximum Duty VIN Max VIN Min Cycle2 ESD Sensitivity Package InformationAbsolute Maximum Ratings Package Brand Information AC Asynchronous Signal Specifications Timing SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle Time Reference Clocks-System Clock Sclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max Unit Power-Up Reset Timing Power-Up Timing1 On-Chip Dram Refresh1 Normal Reset Timing OutputDisable Max AC Signal Specifications Strap Pins DS2-0 Static Pins-Must Be ConstantJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9 Link Port Lvds Receive Electrical Characteristics Link Port Lvds Transmit Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VOD Parameter Description Min Max Unit Link Port-Data Out Timing Link Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In Timing Link Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive Currents Test Conditions Output Disable Time Capacitive Loading Output Enable Time Times Andfall Rise Fall Time Thermal Characteristics for 25 mm × 25 mm Package Thermal CharacteristicsEnvironmental Conditions Parameter Condition Typical Unit Ball Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal Name L0ACKO Sdcke SCLKRAT1L0DATI1N L0DATI3N ID2 TDI TMR0E DS2 Enedreg TCKDS1 CONTROLIMP1 TDO FLAG3 L1CLKINN BGA Data for Use with Surface Mount Design Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December