Main
a
TigerSHARC
Embedded Processor ADSP-TS201S
KEY FEATURES
KEY BENEFITS
ADSP-TS201S
TABLE OF CONTENTS
REVISION HISTORY
GENERAL DESCRIPTION
DUAL COMPUTE BLOCKS
DATA ALIGNMENT BUFFER (DAB)
DUAL INTEGER ALU (IALU)
PROGRAM SEQUENCER
Interrupt Controller
Flexible Instruction Set
DSP MEMORY
EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
Host Interface
Multiprocessor Interface
SDRAM Controller
EPROM Interface
DMA CONTROLLER
Rev. C | Page 8 of 48 | December 2006
Figure 4. ADSP-TS201S Shared Memory Multiprocessing System
LINK PORTS (LVDS)
TIMER AND GENERAL-PURPOSE I/O
RESET AND BOOTING
CLOCK DOMAINS
POWER DOMAI NS
FILTERING REFERENCE VOLTAGE AND CLOCKS
DEVELOPMENT TOOLS
EVALUATION KIT
DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)
ADDITIONAL INFORMATION
PIN FUNCTION DESCRIPTIONS
Table 5. Pin DefinitionsExternal Port Bus Controls
Table 6. Pin DefinitionsExternal Port Arbitration
Table 7. Pin DefinitionsExternal Port DMA/Flyby
Table 8. Pin DefinitionsExternal Port SDRA M Controller
Table 9. Pin DefinitionsJTAG Port
Table 10. Pin DefinitionsFlags, Interrupts, and Timer
Table 11. Pin DefinitionsLink Ports
Table 12. Pin DefinitionsImpedance Control, Drive Strength Control, and Regulator Enable
Table 13. Impedance Control Selection
Table 14. Drive Strength/Output Impedance Selection
Table 15. Pin DefinitionsPower, Ground, and Reference
ADSP-TS201S
STRAP PIN FUNCTION DESCRIPTIONS
ADSP-TS201SSPECIFICATIONS
OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Table 18. Maximum Duty Cycle for Input Transient Voltage
PACKAGE INFORMATION
T
ABSOLUTE MAXIMUM RATINGS
a
TIMING SPECIFICATIONS
General AC Timing
Table 23. Reference ClocksSystem Clock (SCLK) Cycle Time
Table 24. Reference ClocksJTAG Test Clock (TCK) Cycle Time
Table 25. Power-Up Timing
Table 26. Power-Up Reset Timing
Table 27. Normal Reset Timing
Table 28. On-Chip DRAM Refresh
Table 29. AC Signal Specifications
Table 29. AC Signal Specifications (Continued)
Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing
Table 31. Link Port LVDS Receive Electrical Characteristics
Page
Figure 18. Link PortsOutput Clock
LxCLKOUT
LxBCMPO
t
Figure 21. Link PortsTransmission Start
Figure 22. Link PortsTransmission End and Stops
t
t
Figure 23. Link PortsBack to Back Transmission
t
Page
Figure 25. Link PortsData Input Setup and Hold
t
t LDIS t LDIH t LDIS t
These parameters are valid for both clock edges.
OUTPUT DRIVE CURRENTS
VDD_IO=2.63V,40C
VDD_IO=2.5V,+25C
VDD_IO=2.38V,+105C
I
TEST CONDITIONS
t
tDECAY CLV()IL
Figure 35. Output Enable/Disable
90
Output Enable Time
Capacitive Loading
Figure 41. Typical Output Rise and Fall Time (10% to 90%, V
25
LOADCAPACITANCE ( pF)
10
5
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
576-BALL BGA_ED PIN CONFIGURATIONS
Figure 46. 576-Ball BGA_ED Pin Configurations
(Top View, Summary)
Table 35. 576-Ball (25 mm 25 mm) BGA_ED Ball Assignments
Page
Table 35. 576-Ball (25 mm 25 mm) BGA_ED Ball Assignments (Continued)
OUTLINE DIMENSIONS
Nonsolder Mask Defined (NSMD) 0.69 mm diameter 0.56 mm diameter
TOP VIEW BOTTOMVIEW
DETAILA
Figure 47. 576-Ball BGA_ED (BP-576)
ORDERING GUIDE
