Link Ports-Output Clock | Analog Devices ADSP-TS201S specification

ADSP-TS201S

VOD = 0V

LxCLKOUT

tCOJT

tLCLKOP

tLCLKOH tLCLKOL

LxCLKOUT

VOD = 0V

tLDOS

tLDOH tLDOS

tLDOH

Figure 18. Link Ports—Output Clock

VO_P

		CL_P	RL = 100
RL	CL	CL_P	CL = 0.1pF
RL	CL		CL = 0.1pF
			CL_P = 5pF
VO_N			CL_N = 5pF
VO_N		CL_N
		CL_N

LxDATO

VOD = 0V

Figure 20. Link Ports—Data Output Setup and Hold1

1These parameters are valid for both clock edges.

tREO	tFEO
+VODMIN
VOD = 0V
-VODMIN

Figure 19. Link Ports—Differential Output Signals Transition Time

LxCLKOUT

VOD = 0V

LxDATO

VOD = 0V

LxACKI

LxBCMPO

tLACKID

tBCMPOV

Figure 21. Link Ports—Transmission Start

Rev. C Page 32 of 48 December 2006

Page 32

Image 32

Analog Devices ADSP-TS201S specifications Link Ports-Output Clock

Contents

ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 ns Dual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction Set External Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal Space DMA Controller Host InterfaceMultiprocessor Interface Sdram Controller DMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports Lvds Development Tools Power DomainsFiltering Reference Voltage and Clocks Evaluation KIT Additional Information Pin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio Ratio Pin Definitions-External Port Bus Controls ACK T/OD Signal Type Pin Definitions-External Port Arbitration Pin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC Makes Pin Definitions-External Port Sdram Controller LdqmHdqm SDA10 Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1 Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control Selection Pin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Operating Conditions Sclkvref Electrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2 Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand Information Timing Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle Time Reference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max Unit Power-Up Timing1 Power-Up Reset Timing Normal Reset Timing On-Chip Dram Refresh1 AC Signal Specifications OutputDisable Max DS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9 Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VOD Link Port-Data Out Timing Parameter Description Min Max Unit Link Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold Figure Link Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at Strength Output Disable Time Test Conditions Output Enable Time Capacitive Loading Times Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical Unit Ball Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball Assignments Sdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3N DS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINN Surface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December