AC Signal Specifications | Analog Devices ADSP-TS201S specs

ADSP-TS201S

Table 29. AC Signal Specifications

(All values in this table are in nanoseconds.)

Name

Description

ADDR31–0

External Address Bus

DATA63–0

External Data Bus

Memory Select HOST Line

MSH

Memory Select SDRAM Lines

MSSD3–0

Memory Select for Static Blocks

MS1–0

Memory Read

RD

Write Low Word

WRL

Write High Word

WRH

ACK

Acknowledge for Data High to Low

Acknowledge for Data Low to High

SDCKE

SDRAM Clock Enable

Row Address Select

RAS

Column Address Select

CAS

SDRAM Write Enable

SDWE

LDQM

Low Word SDRAM Data Mask

HDQM

High Word SDRAM Data Mask

SDA10

SDRAM ADDR10

Host Bus Request

HBR

Host Bus Grant

HBG

Back Off Request

BOFF

Bus Lock

BUSLOCK

Burst Pin

BRST

Multiprocessing Bus Request Pins

BR7–0

Bus Master Debug Aid Only

BM

I/O Read Pin

IORD

I/O Write Pin

IOWR

I/O Enable Pin

IOEN

Core Priority Access High to Low

CPA

Core Priority Access Low to High

DMA Priority Access High to Low

DPA

DMA Priority Access Low to High

Boot Memory Select

BMS

FLAG3–02

FLAG Pins

3, 4

Global Reset Pin

RST_IN

TMS

Test Mode Select (JTAG)

TDI

Test Data Input (JTAG)

TDO

Test Data Output (JTAG)

3, 4

Test Reset (JTAG)

TRST

7

Emulation High to Low

EMU

ID2–08

Static Pins—Must Be Constant

CONTROLIMP1–08

Static Pins—Must Be Constant

SetupInput (Min)	HoldInput (Min)	OutputValid (Max)	OutputHold (Min)	OutputEnable (Min)	OutputDisable	(Max)	Reference Clock
				1	1
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.0	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	3.6	1.0	1.15	2.0		SCLK
1.5	0.5	4.2	0.9	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	—	—	—	—		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	—	—	—	—		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	—	—		SCLK
—	—	4.0	1.0	—	—		SCLK
—	—	4.0	1.0	1.0	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
1.5	0.5	4.0	1.0	0.75	2.0		SCLK
1.5	0.5	29.5	2.0	0.75	2.0		SCLK
1.5	0.5	4.0	1.0	0.75	2.0		SCLK
1.5	0.5	29.5	2.0	0.75	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
—	—	4.0	1.0	1.15	2.0		SCLK
1.5	2.5	—	—	—	—		SCLK5
1.5	0.5	—	—	—	—		TCK
1.5	0.5	—	—	—	—		TCK
—	—	4.0	1.0	0.75	2.0		TCK6
1.5	0.5	—	—	—	—		TCK
—	—	5.5	2.0	1.15	4.0		TCK or SCLK
—	—	—	—	—	—		—
—	—	—	—	—	—		—

Rev. C Page 28 of 48 December 2006

Image 28

Analog Devices ADSP-TS201S specifications AC Signal Specifications, OutputDisable Max

Contents

ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 ns Data Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction Set External Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal Space DMA Controller Host InterfaceMultiprocessor Interface Sdram Controller DMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports Lvds Filtering Reference Voltage and Clocks Power DomainsDevelopment Tools Evaluation KIT Additional Information Pin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio Ratio Pin Definitions-External Port Bus Controls ACK T/OD Signal Type Pin Definitions-External Port Arbitration Pin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC Makes Pin Definitions-External Port Sdram Controller LdqmHdqm SDA10 Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1 Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control Selection Type at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Operating Conditions Sclkvref Electrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2 Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand Information Timing Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle Time Reference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max Unit Power-Up Timing1 Power-Up Reset Timing Normal Reset Timing On-Chip Dram Refresh1 AC Signal Specifications OutputDisable Max DS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9 Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VOD Link Port-Data Out Timing Parameter Description Min Max Unit Link Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold Figure Link Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at Strength Output Disable Time Test Conditions Output Enable Time Capacitive Loading Times Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical Unit Ball Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball Assignments Sdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3N DS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINN Surface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December