Freescale Semiconductor MPC860T manuals

Freescale Semiconductor MPC860T User Manual

68 pages838.59 Kb

3
Overview
Fast Ethernet Controller Operation
FEC External Signals
4
Parallel I/O Ports
Programming Model
SDMA Bus Arbitration and Transfers
5
Electrical Characteristics
8 ILLUSTRATIONS
9
TABLES
10 TABLES
11 Chapter 1 Overview
- 1.2 Overview
- 1.1 Document Revision History
- 12
- 1.3 Comparison with the MPC860
- 1.4 Features
- - 13
  - 1.4.1 MPC860TBlock Diagram
    - 1-4
    - MPC860T (Rev. D) Fast Ethernet Controller Supplement
    - Figure 1-1. MPC860T Block Diagram
    - 14
  - 1.4.2 SIU Interrupt Conguration
- 151.5 Glueless System Design
  - 16
  - Figure 1-3. MPC860T Serial Configuration
    - 2-1
    - Chapter 2. FEC External Signals
17 Chapter 2 FEC External Signals
- - Table 2-1. FEC Signal Descriptions
- 2.1 Signal Descriptions
- - - 2-2
    - MPC860T (Rev. D) Fast Ethernet Controller Supplement
  - 18 Table 2-1. FEC Signal Descriptions (Continued)
    - 2-3
    - Chapter 2. FEC External Signals
  - 19 Table 2-1. FEC Signal Descriptions (Continued)
    - 3-1
    - Chapter 3. Fast Ethernet Controller Operation
21 Chapter 3 Fast Ethernet Controller Operation
- This chapter discusses the operation of the FEC.
- 3.1 Transceiver Connection
  - Serial-mode connections to the external transceiver are shown in Table 3-2.
    - Table 3-1. MII Signals
- 223.2 FEC Frame Transmission
- 233.3 FEC Frame Reception
- 243.4 CAM Interface
- 3.5 FEC Command Set
- 3.6 Ethernet Address Recognition
- 253.7 Hash Table Algorithm
- 263.8 Inter-Packet Gap Time
- 3.9 Collision Handling
- 273.10 Internal and External Loopback
- 3.11 Ethernet Error-Handling Procedure
  - 3.11.1 Transmission Errors
  - 3.11.2 Reception Errors
    - 3-8 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
    - 28Table 3-4. Reception Errors
29Chapter 4 Parallel I/O Ports
- 4.1 Port D Pin Functions
  - 4-2 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
  - Table 4-1 shows the port D pin assignments.
  - 304.1.1 Port D Registers
    - Port D has three memory-mapped, read/write, 16-bit control registers.
  - 4.1.2 Enabling MII Mode
    - To enable MII mode, do the following: 1. Write 0x1FFF to PDPAR. 2. Write 0x1FFF to PDDIR.
      - Table 4-1. Port D Pin Assignment
31Chapter 5 SDMA Bus Arbitration and Transfers
- 5.1 Overview
- 5.2 The SDMA Registers
  - 5-2 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
  - 325.2.1 SDMA Conguration Register (SDCR)
    - Table 5-1 describes SDCR elds.
      - Figure 5-2. SDMA Configuration Register (SDCR) Table 5-1. SDCR Field Descriptions
33Chapter 6 Programming Model
- 6.1 Overview
- 6.2 Parameter RAM
  - 6-2 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
  - 346.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)
    - Figure 6-1. ADDR_LOW Register
    - Table 6-1. FEC Parameter RAM Memory Map (Continued)
  - 356.2.2 RAM Perfect Match Address High (ADDR_HIGH)
  - 6.2.3 RAM Hash Table High (HASH_TABLE_HIGH)
    - 6-4 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
    - Table 6-4 describes HASH_TABLE_HIGH elds.
  - 366.2.4 RAM Hash Table Low (HASH_TABLE_LOW)
    - Figure 6-4. HASH_TABLE_LOW Register
    - Figure 6-3. HASH_TABLE_HIGH Register Table 6-4. HASH_TABLE_HIGH Field Descriptions
  - 376.2.5 Beginning of RxBD Ring (R_DES_START)
  - 6.2.6 Beginning of TxBD Ring (X_DES_START)
  - 386.2.7 Receive Buffer Size Register (R_BUFF_SIZE)
    - MOTOROLA Chapter 6. Programming Model 6-7
    - Table 6-8 describes R_BUFF_SIZE elds.
  - 396.2.8 Ethernet Control Register (ECNTRL)
    - Figure 6-7. R_BUFF_SIZE Register Table 6-8. R_BUFF_SIZE Field Descriptions
    - Figure 6-8. ECNTRL Register
  - 406.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK)
    - MOTOROLA Chapter 6. Programming Model 6-9
    - and RFINT to notify at the end of frame.
  - 416.2.10 Ethernet Interrupt Vector Register (IVEC)
    - Table 6-10. I_EVENT/I_MASK Field Descriptions
  - 426.2.11 RxBD Active Register (R_DES_ACTIVE)
  - 436.2.12 TxBD Active Register (X_DES_ACTIVE)
  - 446.2.13 MII Management Frame Register (MII_DATA)
  - 466.2.14 MII Speed Control Register (MII_SPEED)
  - 476.2.15 FIFO Receive Bound Register (R_BOUND)
  - 486.2.16 FIFO Receive Start Register (R_FSTART)
  - 6.2.17 Transmit Watermark Register (X_WMRK
  - 496.2.18 FIFO Transmit Start Register (X_FSTART)
    - 6-18 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
    - Table 6-20 describes X_FSTART elds.
  - 506.2.19 DMA Function Code Register (FUN_CODE)
    - Figure 6-19. FUN_CODE Register
    - Figure 6-18. X_FSTART Register Table 6-20. X_FSTART Field Descriptions
      - MOTOROLA Chapter 6. Programming Model 6-19
    - Table 6-21 describes FUN_CODE elds.
  - 516.2.20 Receive Control Register (R_CNTRL)
    - Table 6-21. FUN_CODE Field Descriptions
    - Figure 6-20. R_CNTRL Register
      - 6-20 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
    - Table 6-22 describes R_CNTRL elds.
  - 526.2.21 Receive Hash Register (R_HASH)
    - Figure 6-21. R_HASH Register
    - Table 6-22. R_CNTRL Field Descriptions
      - MOTOROLA Chapter 6. Programming Model 6-21
    - Table 6-22 describes R_HASH elds.
  - 536.2.22 Transmit Control Register (X_CNTRL)
    - Table 6-24 describes X_CNTRL elds.
    - Table 6-23. R_HASH Field Descriptions
    - Figure 6-22. X_CNTRL Register Table 6-24. X_CNTRL Field Descriptions
- 546.3 Initialization Sequence
  - 6.3.1 Hardware Initialization
  - 6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN])
  - 556.3.2.1 Descriptor Controller Initialization
  - 6.3.2.2 User Initialization (after Asserting ECNTRL[ETHER_EN])
- 566.4 Buffer Descriptors (BDs)
  - 6.4.1 Ethernet Receive Buffer Descriptor (RxBD)
    - 57The RxBD format is shown in Table 6-27.
      - MOTOROLA Chapter 6. Programming Model 6-25
  - 586.4.2 Ethernet Transmit Buffer Descriptor (TxBD)
    - MOTOROLA Chapter 6. Programming Model 6-27
    - 59Table 6-29. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued)
61Chapter 7 Electrical Characteristics
- 7.1 DC Electrical Characteristics
- 7.2 AC Electrical Characteristics
- 7.3 Electrical Specications
  - 7.3.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, RX_CLK)
  - 627.3.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
    - MOTOROLA Chapter 7. Electrical Characteristics 7-3
    - Figure 7-2. MII Transmit Signal Timing Diagram
  - 637.3.3 MII Async Inputs Signal Timing (CRS, COL)
    - Figure 7-3. MII Async Inputs Timing Diagram
    - Table 7-3. MII Async Inputs Signal Timing
      - 7-4 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
  - 647.3.4 MII Serial Management Channel Timing (MDIO,MDC)
    - Figure 7-4 shows the MII serial management channel timing diagram.
      - Figure 7-4. MII Serial Management Channel Timing Diagram
      - Table 7-4. MII Serial Management Channel Timing
        MOTOROLA Chapter 7. Electrical Characteristics 7-5
- 657.4 MPC860T Pin Assignments
  - Figure 7-5 shows the MPC860T pin assignments. Pins that support the FEC are shown in black.
    - Figure 7-5. MPC860T Pinout DiagramTop View