Freescale Semiconductor MPC860T user manual FEC Signal Descriptions, Name Pin Description

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc...

Chapter 2

FEC External Signals

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This chapter contains brief descriptions of the MPC860T FEC input and output signals in their functional groups.

2.1 Signal Descriptions

The MPC860T system bus signals consist of all the lines that interface with the external bus. Many of these lines perform different functions, depending on how the user assigns them. The input and output signals, shown in Table 2-1, are identiÞed by their abbreviated names.

		Table 2-1. FEC Signal Descriptions
Name	Pin			Description
	Number
	W15	Interrupt request 7ÑThis input is one of the eight external lines that can request (by means
IRQ7
MII_TX_CLK		of the internal Interrupt Controller) a service routine from the core. See description of
		MII_TXCLK for information about masking			IRQ7.
		MII transmit clockÑInput clock that provides the timing reference for TX_EN, TXD, and
		TX_ER. Note that MII_TXCLK becomes active as soon as the ETHER_EN bit in the Ethernet
		control register (ECNTRL) is set.		must be masked in the system interface unit (SIU).
			IRQ7
PD[15]	U17	General-purpose I/O port D bit 15ÑThis is bit 15 of the general-purpose I/O port D.
L1TSYNCA
		Transmit data sync signal for TDM channel A
MII_RXD[3]
		MII receive data 3ÑInput signal RXD[3] represents bit 3 of the nibble of data to be
		transferred from the PHY to the MAC when RX_DV is asserted.
PD[14]	V19	General-purpose I/O port D bit 14ÑThis is bit 14 of the general-purpose I/O port D.
L1RSYNCA
		Input receive data sync signal to the TDM channel A
MII_RXD[2]
		MII receive data 2ÑInput signal RXD[2] represents bit 2 of the nibble of data to be
		transferred from the PHY to the MAC when RX_DV is asserted.
PD[13]	V18	General-purpose I/O port D bit 13ÑThis is bit 13 of the general-purpose I/O port D.
L1TSYNCB
		Transmit data sync signal for TDM channel B
MII_RXD[1]
		MII receive data 1ÑInput signal RXD[1] represents bit 1 of the nibble of data to be
		transferred from the PHY to the MAC when RX_DV is asserted.

MOTOROLAChapter 2. FEC External Signals2-1

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