Freescale Semiconductor MPC860T Describes Sdcr Þelds, Sdcr Field Descriptions, FRZ Faid RAID, Frz

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

5.2.1 SDMA ConÞguration Register (SDCR)

The SDMA conÞguration register (SDCR), shown in Figure 5-2, is used to conÞgure all 16 SDMA channels. It is always read/write in supervisor mode, although writing to the SDCR is not recommended unless the CPM is disabled. SDCR interacts with the DMA controllers in the FEC. Refer to the MPC860 PowerQUICC UserÕs Manual for more information.

Bit	0	1	2	3	4	5		6		7	8	9	10	11	12		13	14		15
Field									Ñ
Reset							0000_0000_0000_0000
R/W										R/W
Address						(IMMR & 0xFFFF0000) + 0x030
Bit	16	17	18	19	20	21		22		23	24	25	26	27	28		29	30		31
Field	Ñ	FRZ							Ñ						FAID			RAID
Reset	0	0					00_0000_0000									00			00
R/W	R	R/W							R						R/W			R/W
Address						(IMMR & 0xFFFF0000) + 0x030

Figure 5-2. SDMA Configuration Register (SDCR)

Table 5-1 describes SDCR Þelds.

				Table 5-1. SDCR Field Descriptions
Bits	Name			Description
0Ð16	Ñ	Reserved. These bits are reserved and should be cleared.
17	FRZ		Freeze. Determines the action to be taken when the FRZ signal is asserted. The SDMA negates
				and keeps it that way until the FRZ signal is negated or reset occurs.
			BR
		0		The SDMA channels ignore the FRZ signal.
		1		The SDMA channels freeze on the next bus cycle.
19Ð27	Ñ	Reserved, should be cleared for typical applications.
28Ð29	FAID		FEC arbitration ID. Determines FEC arbitration priority for the U bus; 00 for typical applications.
		00		Priority 6 (highest)
		01		Priority 5
		10		Priority 2
		11		Priority 1 (lowest)
30Ð31	RAID		RISC controller arbitration ID. Determines the SDMA channel arbitration ID, which establishes the
		priority level of bus arbitration among modules that can become master of the U bus (01 for
		typical applications). The instruction cache, data cache, SIU, and SDMAs compete for bus
		mastership. Arbitration IDs for all other bus masters are internally Þxed.
		00		Priority 6 (highest)
		01		Priority 5
		10		Priority 2
		11		Priority 1 (lowest)

5-2MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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