Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-1. FEC Parameter RAM Memory Map (Continued)

Address

Name

Description

Section

 

 

 

 

0xE40

ECNTRL

Ethernet control register

6.2.8

 

 

 

 

0xE44

IEVENT

Interrupt event register

6.2.9

 

 

 

 

0xE48

IMASK

Interrupt mask register

6.2.9

 

 

 

 

0xE4C

IVEC

Interrupt level and vector status

6.2.10

 

 

 

 

0xE50

R_DES_ACTIVE

Receive ring updated ßag

6.2.11

 

 

 

 

0xE54

X_DES_ACTIVE

Transmit ring updated ßag

6.2.12

 

 

 

 

0xE80

MII_DATA

MII data register

6.2.13

 

 

 

 

0xE84

MII_SPEED

MII speed register

6.2.14

 

 

 

 

0xECC

R_BOUND

End of FIFO RAM (read-only)

6.2.15

 

 

 

 

0xED0

R_FSTART

Receive FIFO start address

6.2.16

 

 

 

 

0xEE4

X_WMRK

Transmit Watermark

6.2.17

 

 

 

 

0xEEC

X_FSTART

Transmit FIFO start address

6.2.18

 

 

 

 

0xF34

FUN_CODE

Function code to SDMA

6.2.19

 

 

 

 

0xF44

R_CNTRL

Receive control register

6.2.20

 

 

 

 

0xF48

R_HASH

Receive hash register

6.2.21

 

 

 

 

0xF84

X_CNTRL

Transmit control register

6.2.22

 

 

 

 

6.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)

The ADDR_LOW register, shown in Figure 6-1, is written by and must be initialized by the user. It contains the lower 32 bits of the 48-bit address used in the address recognition process to compare with the destination address Þeld of the receive frames.

Bits

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

ADDR_LOW BYTE 0

 

 

 

 

ADDR_LOW BYTE 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE00

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

ADDR_LOW BYTE 2

 

 

 

 

ADDR_LOW BYTE 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-1. ADDR_LOW Register

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Freescale Semiconductor MPC860T user manual RAM Perfect Match Address Low Register Addrlow