Document Revision History | Freescale Semiconductor MPC860T instruction

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc...

Chapter 1

Overview

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This chapter provides an overview of Rev. D of the MPC860T, focussing primarily on the Fast Ethernet controller (FEC). It provides a discussion of its basic features and a general look at how the MPC860T can be implemented. This document is provided as a supplement to the MPC860 PowerQUICC UserÕs Manual.

Note

This supplement documents Rev D silicon of the MPC860T, which includes enhancements made to the original MPC860T. New functionality and changes are shown with change bars and was made available with Rev D MPC860T at 3Q99. This document does not replace the supplement that describes the Rev B.x silicon.

1.1 Document Revision History

Table 1-1 lists signiÞcant changes between revisions of this document.

	Table 1-1. Document Revision History

Document Revision	Substantive Changes

Rev 0.8	Changed the port D pin function multiplexing control bit Þeld name in the ECNTRL register from
	ÔV860TÕ to ÔFEC_PINMUXÕ. See Section Chapter 2, ÒFEC External Signals,Ó and Section 6.2.8,
	ÒEthernet Control Register (ECNTRL).Ó

1.2 Overview

The MPC860T is an enhancement to the MPC8xx family with its incorporation of a Fast Ethernet communication controller. The 10/100 Fast Ethernet controller with integrated FIFOs and bursting DMA is implemented independently, so high-performance Fast Ethernet connectivity can be achieved without affecting the CPM performance.

Like the other MPC860 devices, the MPC860T can be used in a variety of controller applications, excelling particularly in communications and networking products such as routers that provide WAN-to-LAN functionality. The MPC860T, with the addition of the 10/100Mbps Ethernet channel, adds Fast Ethernet to the already broad list of communications support.

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Freescale Semiconductor MPC860T user manual Document Revision History, Overview, Substantive Changes

Contents

Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet Controller Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number Illustrations Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision HistoryOverview Lists signiÞcant changes between revisions of this document Comparison with the MPC860 Features 1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System Design Inc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miitxer L1RSYNCBMiimdc RXD3 MIITXD1 REJECT3MIITXD2 REJECT4 Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver Connection RXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0 FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table Algorithm Collision Handling Inter-Packet Gap Time Internal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception Errors Reception Errors Port D Pin Functions Chapter Parallel I/O Ports Shows the port D pin assignments Enabling MII ModeSignal Function Port D Registers CLK Sdma Registers Bits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAID Address Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory Map RAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow Þelds Hashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field Descriptions Describes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow Þelds Xdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize Þelds Fecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field Descriptions Hberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field Descriptions Ilevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field Descriptions 12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata Þelds Dispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions 17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register 18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart Þelds 19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field Descriptions Descbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field Descriptions Bcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions 23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds 25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware Initialization Step Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting Ecntrletheren Step 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBD RO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data Length TO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field Descriptions Data Xcntrlhbc = Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Num Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal Timing CRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen Txer MII Serial Management Channel Timing Shows the MII serial management channel timing diagram MPC860T Pin Assignments Following pins are marked as spare on Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product