Transmit Watermark Register Xwmrk | Freescale Semiconductor MPC860T

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-17. R_BOUND Field Descriptions

Bits	Name	Description

22Ð29	R_BOUND	Read-only. Highest valid FIFO RAM address.

30Ð31	Ñ	Reserved. Should be written to zero by the host processor.

6.2.16 FIFO Receive Start Register (R_FSTART)

The R_FSTART register, shown in Figure 6-16, is programmed by the user to indicate the starting address of the receive FIFO. R_FSTART marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from X_FSTART to R_FSTART - 4. The receive FIFO uses addresses from R_FSTART to R_BOUND, inclusive.

Hardware initializes R_FSTART with a value that is microcode-dependent after ECNTRL[ETHER_EN] is set. R_FSTART only needs to be written to change the default value.

Bits	0	1	2	3	4	5	6	7		8	9	10	11	12	13	14		15

Field									Ñ

Reset							0000_0000_0000_0000

R/W								Read/write

Addr								0xED0

Bits	16	17	18	19	20	21	22	23		24	25	26	27	28	29	30		31

Field			Ñ			1					R_FSTART						Ñ

Reset							0000_0000_0000_0000

R/W								Read/write

Addr								0xEDC

Figure 6-16. R_FSTART Register

Table 6-18 describes RÑFSTART Þelds.

		Table 6-18. R_FSTART Field Descriptions

Bits	Name	Description

0Ð21	Ñ	Reserved. Note all bits read back as 0 except for 21 which returns a 1.

22Ð29	R_FSTART	Address of Þrst receive FIFO location. Acts as a delimiter between receive and transmit FIFOs.

30Ð31	Ñ	Reserved. Should be written to zero by the host processor.

6.2.17 Transmit Watermark Register (X_WMRK

The X_WMRK register is used to control the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the user to minimize transmit latency (X_WMRK = 0x) or allow larger bus access latency (X_WMRK = 11) due to contention

6-16MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Freescale Semiconductor MPC860T user manual Fifo Receive Start Register Rfstart, Transmit Watermark Register Xwmrk

Contents

MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, Inc Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title Number Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History OverviewLists signiÞcant changes between revisions of this document Document Revision History Features Comparison with the MPC860 1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller Glueless System Design SIU Interrupt ConÞguration Inc Signal Descriptions FEC Signal DescriptionsName Pin Description L1RSYNCB MiimdcRXD3 Miitxer REJECT3 MIITXD2REJECT4 MIITXD1 Freescale Semiconductor, Inc MII Signals Signal Description FEC Signal NameTransceiver Connection This chapter discusses the operation of the FEC Serial Mode Connections to the External Transceiver FEC Frame TransmissionTXD0 RXD0 FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Hash Table Algorithm Rcntrlprom = Inter-Packet Gap Time Collision Handling Ethernet Error-Handling Procedure Transmission ErrorsReception Errors Internal and External Loopback Reception Errors Chapter Parallel I/O Ports Port D Pin Functions Enabling MII Mode Signal FunctionPort D Registers Shows the port D pin assignments Sdma Registers CLK Describes Sdcr Þelds Sdcr Field DescriptionsFRZ Faid RAID Bits Parameter RAM Brießy describes each enter in the FEC parameter RAMFEC Parameter RAM Memory Map Address Name Description Section RAM Perfect Match Address Low Register Addrlow RAM Perfect Match Address High Addrhigh RAM Hash Table High HashtablehighDescribes the Addrlow Þelds Describes the Addrhigh Þelds RAM Hash Table Low Hashtablelow Describes Hashtablehigh ÞeldsHashtablehigh Field Descriptions Hashhigh Beginning of RxBD Ring Rdesstart Beginning of TxBD Ring XdesstartDescribes Hashtablelow Þelds Describes Rdesstart Þelds Receive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Spare Fecpin Etheren Reset MUX Ethernet Control Register EcntrlDescribes Rbuffsize Þelds Rbuffsize Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register Imask Describes Ecntrl ÞeldsEcntrl Field Descriptions Fecpinmux Ethernet Interrupt Vector Register Ivec Rfint to notify at the end of frame10. IEVENT/IMASK Field Descriptions Hberr RxBD Active Register Rdesactive 11 describes Ivec Þelds11. Ivec Field Descriptions Ilevel TxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field Descriptions MII Speed Control Register Miispeed 15 describes Miispeed Þelds15. Miispeed Field Descriptions Dispreamble Miispeed Fifo Receive Bound Register Rbound 17 describes Rbound Þelds16. Programming Examples for Miispeed Register 17. Rbound Field Descriptions Fifo Receive Start Register Rfstart Transmit Watermark Register Xwmrk18 describes Rñfstart Þelds 18. Rfstart Field Descriptions Fifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions DMA Function Code Register Funcode 20 describes Xfstart Þelds20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 Receive Control Register Rcntrl 21 describes Funcode Þelds21. Funcode Field Descriptions Descbo Receive Hash Register Rhash 22 describes Rcntrl Þelds22. Rcntrl Field Descriptions Bcrej Transmit Control Register Xcntrl 22 describes Rhash Þelds24 describes Xcntrl Þelds 23. Rhash Field Descriptions User Initialization before Setting Ecntrletheren Initialization SequenceHardware Initialization 25. Hardware Initialization 27. User Initialization before Setting Ecntrletheren Descriptor Controller InitializationUser Initialization after Asserting Ecntrletheren Step Description 27. User Initialization after Setting Ecntrletheren Buffer Descriptors BDsEthernet Receive Buffer Descriptor RxBD Step RxBD format is shown in Table 27. Receive Buffer Descriptor RxBD Field DescriptionRO1 RO2 Data Length RO1 Ethernet Transmit Buffer Descriptor TxBD 29 describes TxBD Þelds29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSL Xcntrlhbc = Data Freescale Semiconductor, Inc DC Electrical Characteristics AC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcations MII Transmit Signal Timing TXD30, TXEN, TXER, Txclk MII Receive Signal TimingMII Transmit Signal Timing Num Characteristic Min Max Unit MII Async Inputs Signal Timing CRS, COL MII Async Inputs Signal TimingTxen Txer CRS, COL Shows the MII serial management channel timing diagram MII Serial Management Channel Timing Following pins are marked as spare on MPC860T Pin Assignments Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product